Lattice Semiconductor Unveils 3 Wireless IP Cores, Reference Designs

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the availability of three new Intellectual Property (IP) core and reference design products targeting the wireless communications market. The products include RF/IF processing functionality, as well as upgraded support for industry-standard base station connectivity protocols. The designs are optimized to run on the LatticeECP2M[tm] FPGA family in order to provide complete, low cost wireless base station solutions.

“With the advent of Remote Radio Head (RRH) base station topologies and the continuing demand on designers to meet shrinking time-to-market and cost targets, it has become more important than ever for silicon vendors to offer customers complete connectivity and processing solutions,” said Stan Kopec, Lattice corporate vice president of marketing. “The LatticeECP2M[tm] value proposition of a low-cost FPGA fabric combined with embedded high-speed SERDES channels continues to gain traction in the wireless market. With the release of these most recent IP cores and reference designs, Lattice further enhances the value of our LatticeECP2M FPGAs by delivering complete wireless solutions.”

The three designs being released include a Digital Up/Down conversion reference design (DDC/DUC) and IP cores supporting two popular industry standard baseband interface protocols, the Open Base Station Architecture Initiative (OBSAI-RP3-01) and the Common Public Radio Interface (CPRI). The DDC/DUC is a single channel, WiMAX reference design that leverages the embedded DSP blocks of the LatticeECP2M fabric to provide a highly integrated RF card solution. The DUC/DDC package also automatically configures the Lattice ispLeverCORE[tm] IP cores for the Finite Input Response (FIR) filter and Numerically Controlled Oscillator (NCO) functions.

Both the CPRI and OBSAI IP cores have been recently updated to address the expanding landscape of remote radio head base station deployments. The CPRI core is compliant with v3.0 of the specification, supporting 614M, 1.2G and 2.4Gbps data rates by virtue of the embedded SERDES channels in the LatticeECP2M FPGA family. The IP core also has been upgraded to address the concerns of latency variation and enhanced Fast C&M Ethernet control plane requirements that are required for multi-hop remote topologies.

The OBSAI core has been updated to support v4.0 of the specification, which adds a protocol overlay called RP3-01 to the preceding version in order to address the needs of a remote base station topology. Enhancements to the Transport Layer include support for the mapping of RP1 control plane data into an RP3 message, reducing connectivity by allowing both data and control plane messaging to be delivered over a common RP3 electrical link. Also offered is a unique mux/demux capability that further aids in the aggregation and distribution of multiple OBSAI links. Lattice offers development boards and demonstrations to further aid in the design cycle process. These newly announced cores complement other recently announced Lattice products in the wireless solutions segment that include an LTE compliant Turbo Encoder/Decoder from TurboConcept, a jointly developed solution with Linear Technology supporting high speed serial connectivity (JESD204) for A/D converters and support for a Serial RapidIO end point core developed by Praesum Communications.

About the LatticeECP2M Family
The LatticeECP2M FPGA family has redefined the low-cost FPGA product category by providing performance-enhancing features that are typically available only on more expensive competitive high-end FPGAs. The LatticeECP2M family supports logic densities from 20K LUTs up to 100K LUTs, has high performance DSP blocks, supports DDR2 memory interfaces at 533Mbps and up to 840Mbps generic LVDS performance. Some of the high-end features incorporated into the LatticeECP2M family include embedded SERDES I/O and the most on-chip memory in its class. The LatticeECP2M family supports up to 16 channels of embedded SERDES, operating at up to 3.125Gbps, supporting protocols such as PCI Express, Ethernet (1GbE and SGMII), CPRI/OBSAI, SMPTE and JESD204. In addition to the embedded SERDES channels, the LatticeECP2M offers Embedded Block RAM capacity ranging from 1.2 Mbits to 5.3 Mbits, representing up to a 400% increase over competitive low-cost architectures. All LatticeECP2M FPGA family members are now in full production.

About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products. Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP2M, ispLeverCORE and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.