HeedSoft Licenses Nlview Visualization Engine, T-engine Schematic Generator

Concept Engineering announced that HeedSoft S.A.R.L., developer of the TLL[tm] advanced transistor abstraction tool, has signed a worldwide OEM license for Concept Engineering’s Nlview[tm] visualization engine and T-engine[tm] transistor-level schematic generator. Bundling Concept’s Nlview software family into the HeedSoft TLL tool gives design engineers detailed visual feedback about the performed translation process, enabling them to visualize the original transistor-level input circuits and the automatically abstracted, higher-level RTL descriptions.

The Nlview software family automatically generates schematic diagrams for all design levels from register transfer-level (RTL) down to the transistor-level. This provides advanced visualization technology to EDA tool developers who develop debugging cockpits for EDA tools. When integrated with EDA tools, the Nlview engine helps designers of electronic ICs and SoCs to visualize such critical information as circuit structure, critical path circuit fragments, parasitic components, device properties and signal values, so they can more easily and accurately tune designs for low power or for maximum performance and more quickly locate and correct errors in their designs.

“Concept Engineering had the only solution that provided robust and advanced visualization capabilities for both RTL and transistor-level in one integrated environment,” said Philippe Ladagnous, founder, co-director and R&D manager for HeedSoft. “We are already shipping our TLL product with a debugging cockpit that includes their first-class, industry-proven schematic generation and drawing engine.”

HeedSoft’s TLL tool automatically generates a high-level RTL model which exactly matches the original analog or digital transistor-level circuit. As a result, HeedSoft’s abstraction techniques dramatically reduced simulation time, reducing the number of simulator licenses required to perform a greater amount of testing. The automatically generated, higher-level RTL descriptions allow designers to use more validation options than is possible at the transistor level. Nlview and T-engine provide HeedSoft with debugging technology that improves performance and robustness with a rich feature set and support for both RTL and transistor-level at the same time. The result, for HeedSoft customers, is a debugging GUI that provides more insight into the IC design and into the abstraction process.

“HeedSoft’s TLL transistor level abstraction tool offers exciting new options to debug and verify transistor level descriptions,” said Gerhard Angst, president and CEO of Concept Engineering. “We are proud to have been selected to provide advanced visualization technology for HeedSoft’s tool.”

About HeedSoft S.A.R.L.
HeedSoft was created in early 2006 to develop, maintain and commercialize digital circuit validation tools. The two founders, Laurent Boudail and Philippe Ladagnous, after seven years’ experience at TransEda, working on the TLL solution, continue their contribution in the EDA domain through this efficient and unique technology: functional abstraction of electronic circuits. The company’s TLL[tm] advanced transistor abstraction tool, in use by customers such as AMD, transforms complex electronic circuits into an equivalent higher level logic model in Verilog or VHDL. By allowing digital (as opposed to analog) simulation, this abstraction level enables system-in-chip simulation times to be reduced by a factor of several thousand.

About Concept Engineering
Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design tools. The company’s customers are primarily original equipment EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies.