CLK Design Automation, Inc. introduced transistor statistical static timing analysis (TSSTA) for TSMC’s Reference Flow 9.0 to lower design obstacles, improve design margins, and increase 40-nanometer (nm) technology yields. The new Amber[tm] FX Transistor SSTA product, announced separately today by CLK Design Automation, delivers near SPICE accuracy for timing delay and process variance based on TSMC’s advanced manufacturing models.
A year ago, TSMC’s Reference Flow 8.0 introduced the first foundry design methodology to include intra-die statistical timing analysis statistical leakage and statistical timing optimization. TSMC Reference Flow 9.0 supports transistor-level path-based statistical static timing analysis (SSTA) to enhance timing accuracy and reduce the need for pre-characterized cell libraries. These features reduce excess design margins, optimize design performance and improve yields.
“The work between TSMC and CLK Design Automation is part of our Active Accuracy Assurance (AAA) Initiative that we launched in 2007,” said ST Juang, senior director, design infrastructure marketing at TSMC. “Through Reference Flow 9.0, we deliver accuracy without the lag time associated with traditional models and flows. Designers can now validate improved margin and performance prior to tapeout. This is a compelling advantage when designing with advanced 40nm process technologies.”
Enhanced Timing Accuracy
Amber FX SSTA is a cell-based, transistor-level static and statistical timing analyzer. It combines near SPICE accuracy for delay calculation and process variation to evaluate the static timing performance of a set of paths. This analysis is used in conjunction with traditional corner-based STA methods using either the Amber or Amber FX analyzer. Users complete a baseline static timing run, and then select a set of paths to be analyzed using SSTA. The timing and variance of these paths is then recalculated using a fast transistor model (FXM) and delay calculator.
FXM is created from the original SPICE deck for each cell, and derives the variance directly from the process sensitivity data that is captured in the TSMC SPICE parameters. The advantages of FXM are its high accuracy, ease and speed of characterization, and ability to handle a wide range of high-risk timing behaviors (i.e., multiple input switching, non-linear input slopes, voltage drop, functional noise, etc.). The result is that both the nominal delay of a path and its variance calculation has near SPICE accuracy, which is not feasible today with traditional STA tools and methods.
“TSMC’s leadership work on advanced IC processes made it possible for us to develop and deliver TSSTA,” said Isadore Katz, president and CEO of CLK Design Automation. “By combining TSMC’s SPICE models with our next-generation SSTA and transistor models, chip designers now have access to the first transistor-level statistical static timing solution in a foundry-proven design methodology.”
About CLK Design Automation
CLK Design Automation, Inc. develops and markets timing closure solutions used in the design of high-performance microprocessor and advanced semiconductors. Its fully threaded, incremental architecture enables the CLK Amber SA to execute 10 to 100x faster than conventional analysis tools. CLKWorks is a breakthrough solution for variance-tolerant clock tree synthesis and optimization. Headquartered in Littleton, Mass., the company was founded by EDA industry veterans and has received $9 million in venture funding to date.
Amber is trademark of CLK Design Automation.