Bluespec to Showcase FPGA-based Models, Testbenches at DAC

Bluespec[tm] Inc. will demonstrate a synthesizable model and testbench running at 35,000 times faster than event-based simulation and its new development workstation in Booth #2367 during the 45th Design Automation Conference (DAC). DAC runs June 8-13 at the Anaheim Convention Center in Anaheim, Calif. Bluespec is the developer of the only general purpose high-level synthesis solution for synthesizable models, testbenches, control and algorithmic IP and System-on-Chip (SoC) interconnect. Its hardware demo, freed from the constraints of synthesizable RTL subsets, will show an FPGA-based implementation including hardware transactors, a synthesizable testbench, high-level models and AXI® bus components.

An additional highlight will be Bluespec’s new Development Workstation for the design, analysis and debug of high-level models, testbenches and implementations.

Rishiyur Nikhil, Bluespec’s chief technical officer, will present “From Executable Specifications to High-quality Implementations Using Bluespec,” June 8th, from 9:00 a.m. – 9:20 a.m. at the workshop, “High-Level Synthesis: Back to the Future,” in room 208A. Professor Arvind, Bluespec co-founder and board member, will present “HLS as an Enabling Technology: Some Complex Examples” from 1:30 p.m. – 1:50 p.m. at the same workshop.

Rishiyur Nikhil will also be chairing session 23, “Architectural and Precision Optimization in High-Level Synthesis” on Wednesday, June 11th, from 9:00A-11:00A in room 210AB.

Collocated at DAC, Professor Arvind and Rishiyur Nikhil will be giving a tutorial entitled “Hands-on Introduction to BSV (Bluespec SystemVerilog)” on Saturday, June 7, 2008, in room 303B of the Anaheim Convention Center in Anaheim, CA. Details and registration for the tutorial are provided on the MEMOCODE 2008 conference website at:

About Bluespec
Bluespec Inc. manufactures an industry standards-based Electronic Design Automation (EDA) toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. Elevating System-on-Chip (SoC) modeling, verification and implementation with atomic transactions, the only high-level abstraction for hardware concurrency, the general purpose toolset allows ASIC and FPGA teams to reduce development time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found by calling (781) 250-2200.

Bluespec and AzureIP are trademarks of Bluespec Inc.