Aldec, Inc. announced the release of Riviera-PRO 2008.06, a behavioral, structural and mixed HDL language simulator for multi-million gate ASIC and FPGA designs. Riviera-PRO 2008.06 includes Verilog® simulation performance enhancements, increased SystemVerilog support, seamless SystemC/C/C++ and HDL co-debugging in common environment, and new support for SVA and PSL assertions in the Waveform Viewer. Riviera-PRO supports System Level Verification with SystemC and SystemVerilog, Assertions based verification, Open Verification Methodology (OVM), Electronic System Level (ESL), and STARC® based Linting.
Verilog Simulation Performance Speed-Up
Verilog simulation speed at the gate level has been increased up to 2.3X over the previous release. Memory allocation during simulation has been significantly reduced to enable larger solutions on 32- and 64-bit platforms. All mixed language designs will benefit from Verilog performance enhancements.
Aldec Riviera-PRO 2008.06 supports IEEE 1800[TM] SystemVerilog, a unified hardware description and verification language. The tool provides support for SystemVerilog design and verification constructs, incorporating enhanced string support, class inheritance, packages, DPI and libraries.
Seamless Debugging of SystemC/C/C++ and HDL
Ideal for Electronic System Level (ESL) designers, Riviera-PRO offers a new level of integration, enabling SystemC/C/C++ and HDL co-debugging in one simulation environment. Riviera-PRO includes identical procedures for tracing source code, setting breakpoints, viewing objects, and more – no matter what language was used to describe the given portion of the system.
New Assertions Support in Waveform Viewer
The Riviera-PRO interface dramatically increases visibility of assertions and coverage points, enabling their direct, graphical display in a Waveform Viewer and more detailed statistics in enhanced Assertion and Cover Viewers. Assertion-based verification is enabled throughout the Riviera-PRO product.
VHDL 200x Support
Riviera-PRO provides support for the most recent version of the VHDL4.2, IEEE 1076 2008 standard. Riviera-PRO products will include VHDL 200x Standard and IEEE 1076[tm] 2008.
Riviera-PRO is a common-kernel, mixed language, multi-platform simulator for Verilog, SystemVerilog, VHDL, SystemC, C/C++, Assertions and EDIF. Riviera-PRO works in command line mode for maximum speed or in state-of-the-art GUI for enhanced editing, tracing, and debugging capabilities, including code coverage and linting. Riviera-PRO is compatible with industry standards and interfaces with popular EDA products such as Synopsys® SmartModels[tm], Novas[tm], Denali®, MATLAB® and Simulink®.
Pricing and Availability
Riviera-PRO 2008.06 is available today.
Aldec offers a patented technology suite including: design entry, HDL simulators, co-simulation, design rule checking, hardware-assisted verification, co-verification, IP Cores, DO-254 compliance tool sets and engineering specialty solutions.
Riviera-PRO is a trademark of Aldec, Inc.