CoFluent Design, an Electronic System Level (ESL) company focused on delivering model-based software solutions for early system architecture exploration and continuous ESL to implementation verification, is demonstrating a proven solution for closing the validation loop between ESL use cases and cycle-accurate test cases at the 45th Digital Automation Conference (DAC).
Verifying and validating the behavior of a hardware component requires appropriate sequences of stimuli (test cases) and comparison of the results provided by the device under test with the reference results. This verification is often done at the register-transfer level (RTL) and requires up to 70% of the implementation time. A major difficulty consists in describing and applying test cases that are representative of the use of the device in real conditions.
With CoFluent Studio[tm], hardware components and their use cases are specified using graphics and ANSI C/C++ code. Transaction-level SystemC code is automatically generated from these descriptions. The organization (functional pipeline) and performance of components can be analyzed and optimized early in the context of realistic conditions of use by executing abstract models. This removes the need for intricate and effort-prone cycle-accurate and bit-accurate models. These reference transaction-level and use case models constitute executable specifications that guide the hardware implementation.
Combined with a high-level synthesis tool, a full C-based ESL to implementation flow can be achieved. C/C++ algorithms are progressively integrated and refined until functional bit-accurate fixed-point simulation is obtained with CoFluent Studio. They are then translated into synthesizable RTL using a high-level synthesis tool.
Simulation of generated RTL blocks in a dedicated environment delivers precise calibration information that is used for back-annotating the ESL simulation in CoFluent Studio. This validates the reference transaction-level and use case models.
The ESL use cases can validate the cycle-accurate implementation in two ways:
- The SystemC code automatically generated by CoFluent Studio can be used as testbench for driving the simulation of a cycle-accurate model of the component, provided that a SystemC adaptation layer is written for protocols conversion.
- Language-neutral time-accurate test pattern files can be generated from the reference transaction-level model. These files are used to validate the time-accurate behavior of the detailed hardware component model in a dedicated testbench. The test pattern files that are generated are free and purely textual, providing compatibility to any simulation tools.
CoFluent Studio helps hardware designers close the validation loop between ESL executable specifications and use cases, and cycle-accurate implementation and testbench.
About demonstrations and presentations at DAC 2008:
- New ESL Flow Demonstration at Design Automation Conference, Booth #654
- The “High-level Synthesis: Back to the Future” workshop on Sunday June 8 (from 8:30 AM to 5:30 PM, Room 208A) will show the combined use of CoFluent Studio and Mentor Graphics Catapult Synthesis for shortening the path from specification to implementation. It focuses on early architecture validation and high-level synthesis. A full demonstration will be available on the CoFluent Design booth during exhibition hours.
- An example of SystemC testbench generation for a GreenSocs® platform model will be presented at the DAC North American SystemC User’s Group meeting, NASCUG IX, on Sunday June 8 (from 4 PM to 7 PM, Anaheim Hilton Hotel, Ballroom A). A demonstration will be available on the CoFluent Design booth, as well as a demonstration of test pattern file generation for validation with Mentor Graphics ModelSim®.
About CoFluent Design
CoFluent Design provides integrated solutions to bridge the gap between the specification of an electronic system and its implementation. Its CoFluent Studio[tm] ESL modeling and simulation software environment allows developers of electronic devices and chips to:
- DECIDE: Securely predict behavior and performance from partial software and hardware for design validation at all stages
- SHARE: Provide system executable specifications rather than static documents for common hardware / software reference
- CAPITALIZE: Capture projects’ system design expertise in enterprise model libraries for easier and faster innovation
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