Javelin Design Automation Debuts j360 Floorplanning, Prototyping Platform

Javelin Design Automation, provider of System Physical Prototyping[tm] (SPP) EDA solutions for Systems-in-Silicon, unveiled its j360[tm] with TrueFit[tm], TruePlan[tm] and TruePro[tm]: the first-of-its-kind specification-driven virtual silicon prototyping platform tool suite for the enterprise customer. Javelin’s j360 can realistically predict and optimize designs for implementation feasibility and quality-of-results (QoR) in parallel to their design development at the electronic system-level (ESL), register transfer-level (RTL) and netlist stages of design. Its “spec-driven” floorplanning capabilities enable users to “plug and play” data from any abstraction level including spreadsheet, black-box, ESL, RTL, gate-level, LEF/DEF, GDSII and foundry technology models. In this way, users can prototype blocks and chip as they exist in concept and actual design files at any point in the design process.

Understanding and leveraging design and block data as it exists increases both the accuracy and flexibility of the new j360 tool suite. Design objective specifications can be captured and fed-forward into implementation flows to ensure rapid, on-target design closure. The j360 tool suite includes TrueFit, TruePlan and TruePro, which all share an intuitive, user-friendly interface environment and underlying j360 DataWarehouse[tm]. The DataWarehouse can be pre-populated with existing company and 3rd party IP libraries and process technologies. In addition, the j360 suite has integrated extremely fast multi-threaded FloorPlacement[tm], Virtual Route[tm] and Organic Placement[tm] engines that deliver realistic predictions of downstream implementation tool flow results in a fraction of the time of traditional commercial solutions.

About TrueFit[tm]
TrueFit is a silicon-aware chip estimation solution tailored for use by business managers, system chip architects, and project leaders for quick and accurate analysis and estimation of die area, power, cost and I/O utilization at the aggregated level. The user can “drag and drop” actual IP data from the j360 DataWarehouse, or import chip content data from spreadsheets to quickly determine high-level chip estimates automatically that respect underlying silicon processes as well as IP rules and constraints. The user can perform real-world trade-offs, develop design constraints for use later in the design process, and monitor chip metrics against target specs as the design progresses through the development process.

About TruePlan[tm]
TruePlan is tailored for system architects, project leaders and RTL engineers. Instead of waiting until complete and clean RTL/netlists are available, users can now explore and optimize trade-offs in chip architecture, bus topologies, inter-block dataflow, RTL micro-architecture, design structure and/or partitioning with partial or “dirty” RTL/ netlists, in parallel to others developing their respective portions of the chip. This is done by mix-and-matching their plug and play data into the whole to prototype feasible chip-plan options comprised of inter-block connectivity, existing blocks and context-optimized placeholders for blocks that do not yet exist. Users capture their design intent, analyze chip-level and inter-block routes and timing, insert virtual buffers, estimate RTL area and budgets, group and partition logical-to-physical, and plan power.

About TruePro[tm]
TruePro is tailored for physically-aware chip architects, RTL designers, timing leads, and chip integrators to validate that the chip-plans and blocks are physically close-able. This is accomplished by enabling progressive prototyping of the chip-plan and/or blocks-in-chip context as block netlists become available. TruePro’s state-of-the-art, fully multithreaded and multicore Organic Placement and Virtual Route engines provide fast QoR feedback on congestion and timing of these early netlists. This concurrent, hierarchical chip-planning with block-prototyping-in-chip context methodology is called “Progressive Prototyping”. This enables design teams to quickly predict, detect, analyze and fix identified issues in the chip plan well before final netlists are available.

“At 90 nanometers and below, silicon virtual prototyping by the architect and logic designer becomes key to closing timing, area and power in a predictable way,” said Martin Deneroff, head of hardware design and engineering for DE Shaw Research, a company building specialized supercomputers for biomolecular simulation. “Unfortunately, most tools for this purpose require operation by a back-end expert, and they cannot react quickly enough to the exploratory variations needed in early design. Javelin addresses this need with a fast, flexible and accurate prototyping system that is easily operated by the logic designer earlier in the design phase, thereby minimizing issues that would become costly if addressed further downstream and late in the flow.”

“Our company designs and markets extremely low power components for head-worn applications such as hearing aids and wireless headsets,” said Dennis Mitchler, DSP Principal Architect at Sound Design Technologies. “These products have to be extremely optimized to minimize power and area, as well as cost. I use j360 TruePro[tm] to explore and optimize chip architectures and structures quickly and easily because it provides useful feedback on how architecture options will impact physical implementation, and captures our design intent very well. We have been handing-off detailed floorplacements (chip-plan and placed macros-and-gates) to our remote physical design team for chip-finishing and tape-out. Using j360 has helped us to eliminate several potential chip plans that would have resulted in multiple costly iterations and jeopardized our schedule.”

Pricing and Availability
The j360 System Physical Prototyping tool suite is available now and runs on Linux and Windows Operating Systems (OS) for enterprise-wide collaboration. List prices are $350,000 for a foundation bundle containing one each of TrueFit, TruePlan and TruePro. Additional seats of TrueFit, TruePlan and TruePro may be purchased separately.

Javelin at DAC 2008
Javelin will provide product demonstrations of j360 with TrueFit, TruePlan and TruePro at the 45th Design Automation Conference (DAC), June 9-12, 2008, in booth # 541 in Anaheim, California. To learn more, or to reserve time at DAC, please send email to dac@javelin-da.com or call +1.408.741.8288.

About Javelin Design Automation
Javelin Design Automation was founded in July of 2004 to provide System Physical Prototyping[tm] (SPP) EDA solutions for Systems-in-Silicon. The company’s mission is to enable design teams to build physically optimized chips by delivering quality physical design feedback quickly from the earliest specification and architectural stage in the ASIC and SOC development cycle. Using Javelin solutions, engineering teams can make better-informed design decisions, maximize their productivity and design concurrently to shorten design cycles, and reduce project costs.