Apache Design Solutions will host a hands-on tutorial at this years’ 45th Design Automation Conference (DAC), titled “IP Validation for Macro and Embedded SoC.” The tutorial gives attendees first-hand experience in running Apache’s products for validating embedded macro, analyzing full-chip power including package, and generating portable power delivery network model for co-design.
Hands-on-Tutorial titled “IP Validation for Macro and Embedded SoC“
Design Automation Conference
Anaheim Convention Center
2:00 p.m. – 5:00 p.m., PDT
Monday, June 9, 2008
Specifically the tutorial will cover the following:
- Block-level power analysis of a full-custom IP from Virage Logic using RedHawk-MMX
- Package model extraction using PakSi-E
- Full-chip power analysis including validated custom IP and package models using RedHawk-EV
- Chip Power Model generation using RedHawk-CPM
About Apache Design Solutions
Apache delivers the leading power signoff solution adopted by 80% of the top IDM, fabless semiconductor, and foundries and a complete platform for silicon integrity of low-power, high-performance system-on-a-chip (SoC) designs. Apache’s innovative platform considers multiple noise sources that impact the design—such as power, signal, package/system IO, substrate, and temperature—and enables designers to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon and/or system. Apache’s vendor-neutral solution supports any industry-standard physical design flow and is certified by TSMC and Common Platform Reference Flows. Apache is a global company with R&D centers and direct sales/support offices worldwide.
Apache Design Solutions, NSPICE, RedHawk, PakSi-E, PakSi-TM, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.