Certess, Inc., the provider of functional qualification tools for systems on a chip (SoCs) and intellectual property (IP) blocks, will partner with STMicroelectronics and Brian Bailey Consulting to give a hands-on tutorial on the functional verification and integration of design IP at the 45th annual Design Automation Conference (DAC 2008) in Anaheim on June 9th. Attendees will gain hands-on experience in setting up Certess’ Certitude for an existing verification environment, analyzing specific verification weaknesses and improving verification strategy.
Certess, Inc., STMicroelectronics and Brian Bailey Consulting
Hands-on-Tutorial entitled “Elevating Confidence in Design IP Through Mutation-based Analysis Technology“
Room 213D, Design Automation Conference, Anaheim Convention Center, Anaheim, California
9:00 am to noon, PDT, Monday, June 9, 2008
Reuse of design IP has taken center stage in the effort to enable today’s SoC design. One of the most critical of these challenges is the functional verification of design IP and its integration into a SoC.
STMicroelectronics and Certess formed a partnership to identify issues in the verification of design IP that resulted in the advent of Certitude, an innovative verification solution using mutation-based analysis. Certitude delivers greater visibility into functions of the design IPs which are not sufficiently verified. Certitude also highlights areas of the design for which checking is insufficient as well as features for which tests do not exist. It also provides an overall measure of verification completeness. This tutorial will focus on how designers can improve their existing verification strategies, providing experience in setting up Certitude for an existing verification environment and analyzing specific verification weaknesses.
Certess, Inc. is the only electronic design automation company providing functional qualification products for companies that create and integrate complex design blocks or intellectual property (IP). The company’s technology provides design and verification engineers with an objective way to evaluate and improve the completeness of the verification environment, resulting in a shorter and more predictable process to integrate SoC designs and ensure high quality designs. The company is headquartered in Campbell, CA.