Verific Comments on Open Source Release of Synopsys VMM Methodology

Verific Design Automation announced ongoing support for the VMM methodology, originally developed by Synopsys and released into the public domain today. As the primary supplier of SystemVerilog, Verilog and VHDL software front ends to electronic design automation (EDA), field programmable gate array (FPGA) and semiconductor vendors, Verific has offered VMM support in its SystemVerilog analyzer and elaborators since 2006. It was an early VMM Catalyst Member.

Notes Rob Dekker, Verific’s founder and president: “We applaud this move by Synopsys because it eases adoption by other EDA tools. From the outset, it has been important for us to make sure we could parse and analyze the VMM library so that our customers — EDA tool developers — could support it in their end-user tools.”

Previously, the drawback was the need for a separate license from Synopsys to enable vendors to include the VMM library with their tools and the library needed to be distributed in binary format. This move takes away the hassle because Synopsys has made VMM available under the Apache open source license model. Anyone now can download and utilize the VMM library to its fullest extent.

“If an EDA tool has a Verific-powered SystemVerilog front end, the parser will analyze any RTL description incorporating VMM,” adds Dekker.

Verific’s products serve as the front end to the most popular design automation tools for exploring, navigating, analyzing, documenting, synthesizing, simulating, and modifying designs. Its tools include SystemVerilog, Verilog and VHDL analyzers and elaborators, as well as a netlist oriented object database. All are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and come with support and maintenance.

The Verific product line will be showcased during the 45th Design Automation Conference (DAC) in booth #655 June 9-12 at the Anaheim Convention Center in Anaheim, Calif.

About Verific Design Automation
Verific Design Automation, with offices in Kolkata, India, and Alameda, Calif., is a leading provider of SystemVerilog, Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com.

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