Virage Logic Corporation (NASDAQ: VIRL), the semiconductor industry’s trusted IP partner and pioneer in Silicon Aware IP[tm], announced its Intelli[tm] DDR2/3 PHY+DLL, an all-digital PHY+DLL high performance DDR solution. Supporting speeds of up to 1066 Mbps in 65-nanometer (nm) G processes, the all-digital Intelli DDR2/3 PHY+DLL achieves performance and resolution levels that were previously only possible with analog solutions. Unlike all-digital solutions, analog solutions mandate costly silicon validation, with potential silicon re-spins, and therefore typically translate into longer time-to-market.
Virage Logic’s Intelli DDR2/3 controller and PHY+DLL provide a flexible and advanced solution ideal for application specific integrated circuit (ASIC) and System-on-Chip (SoC) designers requiring a reduced area, high performance DDR memory interface. Delivered in an all-digital solution, the Intelli DDR2/3 controller and PHY+DLL are a low-risk investment, providing designers with benefits such as faster time-to-market, higher data throughput efficiency, lower system costs, less power usage and a superior first-time silicon success rate.
“As the semiconductor industry’s trusted IP partner, designers trust Virage Logic to deliver superior IP solutions and our high performance DDR2/3 PHY+DLL in an all-digital implementation definitely lives up to this high standard,” said Kamalesh Ruparel, vice president and general manager of Virage Logic’s application specific IP (ASIP) business. “The Intelli DDR2/3 PHY+DLL not only delivers very high resolutions with an all-digital implementation, but it also provides a significant time-to-market advantage because its standard-cell architecture enables easy design portability across different foundries and process nodes with a high first-time silicon success rate. In contrast, traditional analog-based solutions mandate silicon validation, with potential silicon re-spins, to ensure correct functionality.”
Because of its unique patent-pending architecture, the all-digital Intelli DDR2/3 PHY+DLL is able to achieve the resolutions required to support data rates of up to 1066 Mbps on 65nm G processes, making it a versatile solution for reduced power in a broad range of high performance applications including networking, video, graphics and portable electronics. Its standard cell architecture and digital implementation enable it to integrate seamlessly with digital SoC design flows and allow significant ease of portability to any process node for any foundry.
The Intelli DDR2/3 controller’s advanced architecture allows much higher data throughput efficiency than older architectures provided by competing solutions. Such high efficiencies enable designs to operate at lower frequencies, resulting in lower power consumption and bill of materials costs, which translates into lower system costs.
The Intelli DDR controller and PHY+DLL support single data rate JEDEC standard SDRAM and Mobile SDRAM, double data rate JEDEC standard DDR1/2, DDR2/3, and MobileDDR as well as various multi-protocols.
Pricing and Availability
The Intelli DDR2/3 PHY+DLL all-digital solution for the 65nm G process is available now with pricing starting at $180,000.
About Virage Logic’s Application Specific IP (ASIP) Solutions
Virage Logic’s ASIP product portfolio is designed to meet the highest quality and performance standards for functional IP and contains application specific functional IP targeted to a variety of market requirements for high performance, low power, and low gate count. The ASIP products are commonly based on Virage Logic’s proprietary and patented logic libraries, routing methodology, and cell architecture.
Virage Logic’s Intelli[tm] DDR memory interface solutions include a memory controller and the related PHY and DLL with advanced features to deliver high performance in a minimum die area and with low power dissipation. The solutions are architected to enable optimal size while providing customers with the ability to achieve the maximum performance and minimal power targets with the added flexibility of advanced feature selection. The Intelli DDR solutions are implemented in several SDR and DDR protocols, including SDRAM and Mobile SDRAM, as well as MobileDDR, DDR1 and DDR2 at several foundries on a variety of process nodes.
About Virage Logic
Founded in 1996, Virage Logic Corporation rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. The company’s Silicon Aware IP[tm] offering (embedded memories, logic libraries and I/Os) includes silicon behavior knowledge for increased predictability and manufacturability. Through its acquisition of Ingot Systems in 2007, the company expanded its product offering to include Application Specific IP (ASIP) solutions such as Double Data Rate (DDR) Memory Controllers and design services. The highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated device manufacturers (IDMs) and fabless customers. The company uses its FirstPass-Silicon Characterization Lab[tm] for certain products to help ensure high quality, reliable IP across a wide range of foundries and process technologies.