Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, announced the formation of a broad industry alliance program focused on better integration of the various members of the semiconductor supply chain. The program, called SpyLinks[tm], will leverage Atrenta’s industry standard SpyGlass® product suite and the company’s emerging 1Team® product suite to provide comprehensive support for communication of design quality and design intent between members of the semiconductor supply chain. The ultimate goal of the program is to promote the benefits of Early Design Closure throughout the semiconductor community. Atrenta has appointed Piyush Sancheti, senior director of business development at Atrenta, to manage the program.
SpyLinks will have five primary focus areas:
- System development
- Semiconductor IP
- Application specific integrated circuits (ASIC)
- Electronic design automation (EDA)
The system and semiconductor IP alliances will initially target communicating design quality and intended field of use information for system architectures and semiconductor IP. ASIC alliances will formalize hand-off methods at the register transfer language (RTL) level. EDA alliances will provide smooth integration of the various SpyGlass Early Design Closure capabilities with physical implementation flows, and foundry alliances will assist with the propagation of manufacturing effects upstream (to RTL) for advanced process nodes.
“Atrenta has been working with system providers for many years. We are cooperating with foundries, several top-tier ASIC providers, IP developers and EDA suppliers as well,” said Piyush Sancheti. “All of these engagements have resulted in better quality handoffs and smoother IC implementation. Formalizing these programs will provide a substantially improved level of visibility and support for our alliance partners, worldwide. I look forward to building our SpyLinks program to facilitate that process.”
“As a leading supplier of semiconductor IP, quality is paramount,” said Brian Gardner, vice president of IP products at Denali. “Through the use of SpyGlass, we can ensure that our DDR memory IP meets broadly accepted industry standards, ensuring its successful deployment.”
“At IPextreme, we partner with the world’s leading semiconductor companies to commercialize their internal IP for broad external licensing. Our focus is on quality, completeness and ease of use in order to minimize the integration effort by customers,” said Pierre-Xavier Thomas, vice president of engineering at IPextreme. “We have standardized our IP inspection process and methodology on Atrenta’ s SpyGlass platform, leveraging its broad set of technologies for RTL design.”
“Through its technology and partnerships, Magma demonstrates its commitment to helping customers improve the quality and turnaround time of their most challenging designs,” said Yatin Trivedi, director of industry partnership programs at Magma. “By working with Atrenta through the SpyLinks program we can ensure our mutual customers start with the best RTL and design constraints and end with high-yielding, working silicon in the shortest time.”
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 140 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure.
Atrenta, the Atrenta logo, SpyGlass, 1Team, and Early Design Closure are registered trademarks of Atrenta Inc.