Real Intent Inc., the leading supplier of verification software for electronic design, announced that the newest release of the company’s EnVision[tm] family of verification software will be demonstrated at the Design Automation Conference (DAC) 2008, Booth 2540, with significant productivity improvements, called Speed3. Speed3 refers to speedups from invocation to verification signoff and includes speed of setup, speed of analysis and speed of debug. These improvements can lead to 4x to 10x faster verification signoffs for typical designs when compared to any alternatives.
“The EnVision family of software delivers verification confidence faster because of our high levels of automation, complete error coverage and focus on performance,” said Rich Faris, Vice President of Marketing and Business Development at Real Intent. Faris continued, “Customers consistently tell us that the time to discover and fix their first design bug is faster in Real Intent products than other solutions.”
About Real Intent’s EnVision Family
Meridian CDC[tm] verification software has been enhanced to support gate-level designs of millions of gates. Because of this, Clock Domain Crossing (CDC) verification can be applied to the design after synthesis, scan chain insertion and back-end processing modifications are complete. This eliminates CDC errors caused by design changes between the Register Transfer Level (RTL) and the gate-level design representations. Meridian CDC accepts native Tool Control Language (Tcl) and Synopsys Design Constraints (SDC) as input and includes enhanced setup checks, so the design’s inputs, outputs and clocks are quickly and accurately represented, and bugs can be found faster than before.
Ascent, all-in-one automatic verification software, offers sequential formal bug hunting, and lint analysis that checks the syntax and semantics of an RTL design. Ascent is truly all-in-one, since it includes all the engines and features needed to provide feedback on bugs with detailed signal tracing at no extra charge. It can find bugs before simulation starts, minimizing the nightmare of full-chip functional debugging.
Conquest, static, formal Assertion-Based Verification (ABV) software, works with Ascent and complements functional simulation during early functional verification. It catches the most complex corner-case bugs and is especially powerful when used with designs with a large degree of concurrency. Bugs are visualized for the user in an assertion debug environment for faster and easier functional debug closure.
PureTime is the most accurate verifier for SDC, such as false and multi-cycle path constraints. Full sequential analysis is employed for high accuracy, for analysis of either RTL or structural netlists plus SDC. PureTime reads TCL natively, so editing of users’ TCL isn’t required, and is glitch aware, so that errors due to glitches cannot creep into a design.
About Real Intent
Real Intent is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent’s products dramatically improve the functional verification efficiency of leading edge application specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses, including AMD NVIDIA, and NEC Electronics use Real Intent software. Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, e-mail: firstname.lastname@example.org.
EnVision, Meridian CDC, Conquest, Ascent, PureTime, are trademarks of Real Intent, Inc.