STARC STARCAD-CEL 2.0 Features Sequence PowerTheater, CoolTime Tools

Sequence Design, the EDA leader in Design for Power (DFP) solutions, announced that its PowerTheater and CoolTime low-power tools have been integrated into the latest release of the Japanese Semiconductor Technology Academic Research Center (STARC) advanced design flow, STARCAD-CEL Version 2.0. STARCAD-CEL Version 2.0, addressing the challenges of very advanced process technologies including 65nm and 45nm, has been updated to emphasize low-power design, particularly RTL power analysis and reduction, and power integrity at physical implementation. The STARCAD-CEL Version 2.0 design methodology is shared by the leading Japanese semiconductor companies that comprise STARC’s membership as a standard digital design platform.

“It is vital to control power in the earliest stages of the design,” said Nobuyuki Nishiguchi, Vice President and General Manager, Development Department-1 at STARC. “This requires the accurate RTL power analysis and power reduction capabilities provided by a proven tool such as Sequence’s PowerTheater.”

Sequence’s CoolTime, the industry’s most accurate power integrity analysis and optimization solution, has also been validated for STARCAD-CEL Version 2.0. Nishiguchi praised CoolTime’s ability to significantly reduce both dynamic voltage drop and leakage power in advanced designs.

“It is indeed an honor to have been associated with the STARC team for over four years in creating reference flows for the Japanese design community,” said Vic Kulkarni, President & CEO of Sequence Design. “Their technical guidance has been very valuable to our R&D team in shaping the DFP product line. We are looking forward to many years of collaboration ahead as we embark on solving the sub-45nm power management challenges in SoC designs.”

About PowerTheater/PowerTheater-Explorer
PowerTheater is the industry’s first RTL power analysis and power prototyping solution with the singular ability to accurately analyze power at RTL and support power management techniques such as voltage islands, mixed voltage threshold, power gating, and clock gating. PowerTheater recently added support for the Si2 CPF standard along with the following new features:

  • Control all aspects of running PowerTheater through a single Tcl-based command file
  • Identify high-power windows utilizing comprehensive simulations from hardware accelerators
  • Compute full-chip, gate-level power efficiently using RTL simulations
  • Prevent voltage-drop related test and functional failures by automatically identifying critical vectors from multiple simulations

PowerTheater-Explorer is an innovative capability that adds state-of-the art power visualization and debug features for fast, interactive RTL power analysis. A new SmartSource Viewer allows designers to determine hot spots in the design, to visualize, debug and interactively analyze a design’s power consumption. The hierarchical RTL power tree display shows hot spots that can be cross-probed to schematics, showing connectivity and indicating how activity is moving through the design and how instances impact one another. These results can be displayed and analyzed at RTL, gate, or mixed levels of abstraction. SmartSource also provides a dedicated view of the clock tree for fast analysis and tracing of clock nets in the design.

About Cool Products
Sequence’s Cool Products family – CoolTime, CoolPower, and CoolCheck – cut design closure times by preventing time-consuming iterations between separate timing, SI, power analysis and optimization tools. CoolTime, the industry’s most accurate dynamic voltage drop analysis and optimization solution, concurrently analyzes timing, signal integrity, static IR drop, and electromigration. CoolPower includes automated power, timing, and signal integrity optimization features. Both leakage and dynamic power can be automatically optimized using CoolPower’s multi-Vt cell swapping and cell resizing, and its MTCMOS power gating optimization slashes leakage power up to 100X or more. CoolCheck enables effective power grid debug early in the flow with a fast vectorless technique for finding high resistive connectivity of standard cells and macros.

The Semiconductor Technology Academic Research Center (STARC) was established in December 1995 with investment from Japan’s leading semiconductor suppliers to reinforce semiconductor design capability. Since its inception, STARC has been conducting joint research with universities and the semiconductor industry to strengthen the bases of research in the field of semiconductor technology at domestic universities. The outcomes of these activities are utilized industry-wide in Japan through the transfer of technologies to investing companies to help their businesses, the documenting of technical standards, and the licensing of technologies to partner companies for commercialization. Headquartered in Shin Yokohama, Japan, STARC is co-funded by 11 member companies including Fujitsu Microelectronics Limited, Matsushita Electric Industrial Co., Ltd., NEC Electronics Corporation, Oki Electric Industry Co., Ltd., Renesas Technology Corporation, Rohm Co., Ltd., Sanyo Semiconductor Co., Ltd., Seiko Epson Corporation, Sharp Corporation, Sony Corporation, and Toshiba Corporation.

About Sequence
Sequence Design’s Design For Power (DFP) solutions accelerate the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence’s power and signal-integrity software give customers the competitive advantage necessary to excel in aggressive technology markets.