Technical Working Group Releases DDR PHY Interface Specification 2.0

Denali Software, Inc., as one of the DDR PHY Interface (DFI) specification participating members including ARM, Denali, Intel, and Samsung, announced the release of the new DFI specification version 2.0. The collaborative technical working group, which includes representatives from these companies, delivered several improvements and enhancements in this latest version of the DFI specification. This version of the specification extends support to include DDR1, DDR2, Mobile, and DDR3 memory; adds read, write, and gate training interfaces; and improves upon the interoperability features between the memory controller and a DDR PHY. Chip architects, memory controller vendors, and PHY providers can utilize the new specification to speed their DDR memory system design and integration, and reduces the significant verification costs.

“DDR3 created some technical challenges for this industry collaboration. The team rose to the task, and the result is a specification that ensures interoperability and high performance,” said Brian Gardner, vice president of IP products at Denali.

The DFI specification 2.0 is available through a click-thru license. The official version of the specification has been based on the 1.0 foundation of the common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs. This specification allows designers a standard that has wide industry acceptance and ensures that the controller and PHY will work optimally together and no changes will be required to the hardened logic, resulting in reduced cost, time-to-market, and increasing reusable system IP.

“As many designers are migrating from DDR2 to DDR3 technologies to take advantage of the performance, this places a massive load on the controllers and increases the importance of a standard interface between the controller and PHY,” said Bryan Jones, Corporate External IP Management, Mobility Group for Intel Corporation. “The contributions from the technical team help to increase momentum and opportunities, and we look forward to furthering the usage of this specification within the industry.”

About the DFI Specification
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices.

About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions and platforms for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry.