Mentor Graphics Corporation (Nasdaq: MENT) announced that Toshiba Corporation has selected the Calibre® DFM Platform for its Device Extraction Flow aimed at controlling manufacturing variability at 45 nanometers (nm) and beyond. “Taking actions at the design stage to minimize manufacturing variability is essential to maintaining competitive advantage at advanced process nodes,” said Dr. Fumitomo Matsuoka, senior manager of Advanced Logic Technology Department, System LSI Division at Toshiba.
Calibre solutions are helping Toshiba meet its objectives by providing detailed device parameters based on accurate simulation of the lithographic process window and specific device interactions at very small geometries. Toshiba has been addressing manufacturing variability issues with close cooperation between engineers in their design and device divisions. Their goal was to develop an advanced systematic device extraction flow integrated with its lithography flow that could provide more accurate transistor models incorporating precise effects that become significant at 45nm and smaller nodes. Toshiba adopted the Calibre DFM platform as a key technology in its variability-aware design methodology due to its high accuracy and compatibility with Toshiba’s overall flow.
The Calibre DFM solution includes the Calibre LFD[TM] (Litho-Friendly Design) capability which is fully integrated with new Calibre LVS ADP (Advanced Device Parameter) features, allowing critical device dimensions to be extracted from the LFD-modeled contour geometries to determine a set of equivalent effective dimensions for the devices. The resulting device parameters, which reflect actual as-built device shapes, can then be plugged into a SPICE model to produce an accurate timing simulation of how the real device will work. For drawn parameters, the Calibre LVS component is compliant with the latest industry standard models and includes foundry-specific models for handling advanced stress effects. The combination of the Calibre LFD and LVS capabilities provides a complete and integrated solution that improves SPICE simulations by providing more accurate results that better reflect actual silicon performance.
“Toshiba is leading the way to the next stage of DFM which involves going beyond eliminating catastrophic defects and addressing the issues that affect parametric yield,” said Joseph Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “As foundries and EDA vendors work together to accurately model the manufacturing process at advanced nodes, we can have a substantial impact on overall device yield and performance.”
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $875 million and employs approximately 4,350 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Mentor Graphics and Calibre are registered trademarks and LFD is a trademark of Mentor Graphics Corporation.