Design Automation Conference Features Six Full Day of Tutorials

The Design Automation Conference (DAC) will offer six educational, full day tutorials focused on a variety of design methods. The tutorials will be held Monday, June 9 and Friday, June 13 at this year’s DAC, running from June 8-13 at the Anaheim Convention Center, Anaheim, Calif. The tutorials will provide middle management and design engineers an in-depth look at some of the most difficult and fascinating areas of electronic design, while bringing together industry professionals and experts to address key trends and issues facing today’s EDA industry.

“The full-day tutorials are a unique opportunity for an intensive, accelerated training on a specific subject in depth. It is also an ideal venue for networking with peers who may be solving similar problems,” said Narendra Shenoy, 45th DAC Tutorial Chair. “We encourage design engineers, CAD developers, managers in design and EDA companies to consider attending a full day tutorial this year!”

Full Day Tutorials

Bridging a Verification Gap: C++ to RTL for Practical Design
Monday, June 9 from 9 a.m. to 5 p.m. in room 210AB
This tutorial will focus on describing the practical approaches to design by using high level synthesis technology to create the RTL description and formal verification technology to verify the RTL. It will provide attendees with an in-depth look into some of the technologies from the tools perspective and provide three separate user perspectives.

Vinod Kathail – Synfora, Inc., Mountain View, Calif.
Mike Keating – Synopsys, Inc., Mountain View, Calif.
Alfred Koelbl – Synopsys, Inc., Hillsboro, Ore.
Kelvin Ng – NVIDIA Corp., Santa Clara, Calif.
Emmanuel Chiaruzzi – STMicroelectronics, Grenoble, France
Kees Vissers – Xilinx, Inc., San Jose, Calif.

Programming Massively Parallel Processors: the NVIDIA Experience
Monday, June 9 from 9 a.m. to 5 p.m. in room 209AB
Attendees participating in this tutorial will gain knowledge necessary for developing applications software for processors with parallel computing resources. This tutorial will provide an educational tour and in-depth view into the NVIDIA architecture, the recent advances in software development for this architecture and examples of EDA applications that benefit from such devices.

Wen-mei W. Hwu – University of Illinois, Urbana-Champaign, Ill.
David Kirk – NVIDIA Corp., Santa Clara, Calif.
Damir A. Jamsek – IBM Corp., Austin, Texas

Robust Analog/Mixed-signal Design
Friday, June 13 from 9 a.m. to 5 p.m. in room 208AB
This tutorial will address the art of analog design, presenting a perspective on the challenges facing analog/mixed-signal (AMS) designers, while offering insights into designing robust analog circuits.

Jaeha Kim – Rambus, Inc., Los Altos, Calif.
Trent McConaghy – Solido Design Automation, Inc., Saskatoon, Ontario, Canada
Ken Kundert – Designer’s Guide Consulting, Los Altos, Calif.
Radu Zlatanovici – Cadence Design Systems, Inc., Berkeley, Calif.

DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction
Friday, June 13 from 9 a.m. to 5 p.m. in room 210 AB
In this tutorial, the speakers will explore the effects of DFM in current and next generation technology nodes and approaches for mitigation, providing a holistic approach in analyzing and addressing different effects in sub-45nm technology.

Puneet Gupta – University. of California, Los Angeles, Calif.
Dureseti Chidambarrao – IBM Corp., Hopewell Junction, N.Y.
Praveen Elakkumanan – IBM Corp., Hopewell Junction, N.Y.
Lars Liebmann – IBM Corp., Hopewell Junction, N.Y.
Diana Marculescu – Carnegie Mellon University, Pittsburgh, Pa.
Nagesh Tamarapalli – Advanced Micro Devices, Inc., Bangalore, India

Low Power Techniques for SoC Design
Friday, June 13 from 9 a.m. to 5 p.m. in room 209AB
Based on the bestselling book Low Power Methodology Manual by Mike Keating et al., and subsequent research, the authors will provide participants with various strategies to minimize the static and dynamic power in a design. The tutorial will also include a discussion of Dynamic Voltage and Frequency Scaling with measured results from silicon.

Robert Aitken – ARM, Sunnyvale, Calif.
Mike Keating – Synopsys, Inc., Mountain View, Calif.
David Flynn – ARM, Cambridge, United Kingdom
Alan Gibbons – Synopsys, Inc., Reading, United Kingdom
Nobuyuki Nishiguchi – STARC, Yokohama, Japan
Kaijian Shi – Synopsys, Inc., Dallas, Texas

System Level Design for Embedded Systems
Friday, June 13 from 9 a.m. to 5 p.m. in room 210CD
This tutorial will provide attendees with a comprehensive introduction to using system-level design techniques for high-productivity hardware and software embedded systems development. This tutorial will examine each stage of the design process and will include techniques focusing on multi-domain simulation, rapid-prototyping, hardware deployment, platform dependant and independent design and the inclusion of implementation effects in high-level models.

Mike Woodward – The MathWorks, Inc., Natick, Mass.
Chris Dick – Xilinx, Inc., San Jose, Calif.
Jim Hwang – Xilinx, Inc., San Jose, Calif.
Stephen Koffman – Boeing, El Segundo, Calif.
Alberto Sangiovanni-Vincentelli – University of California, Berkeley, Calif.

The registration fee for each tutorial is $125 for student ACM members, $300 for ACM and IEEE members and $400 for non-members and includes coffee breaks and tutorial notes. For more details on DAC’s full day tutorials, and to register please visit www.dac.com or call 1-800-321-4573 in the U.S. to request registration materials. The advance conference registration discount deadline is May 19, 2008.

About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for Electronic Design Automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,500 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight is its Exhibition and Suite area with approximately 250 of the leading and emerging EDA, silicon and IP providers. The conference is sponsored by the Association for Computing Machinery’s Special Interest Group on Design Automation (ACM/SIGDA), the Circuits and Systems Society and Council on Electronic Design Automation of the Institute of Electrical and Electronics Engineers (IEEE/CASS/CEDA) and the Electronic Design Automation Consortium (EDA Consortium).