Verilog Netlist Parser Integrates with Concise Logic Optimization System

Verific Design Automation said that Concise Logic, provider of transistor-level optimization software and standard cell libraries, has integrated its Verilog netlist only parser with the Concise Logic Optimization System. According to Mike Bohm, Concise Logic’s chief technology officer (CTO), Verific helped accelerate product development and set the stage for the next phase. “I’ve had the opportunity to work with the Verific R&D team on two prior projects involving RTL parsing, and was pleasantly surprised when I found out that they now also ship a netlist-only parser, together with their netlist database. Using Verific’s netlist parser helped us to get development of our Concise Optimization Tool quickly off the ground, and has us fully prepared for future expansion into RTL support.”

Verific’s products serve as the front end to the most popular Electronic Design Automation (EDA) tools for exploring, navigating, analyzing, documenting and modifying designs. Its Verilog Netlist Only Parser reads a Verilog structural netlist into Verific’s hierarchical database, without creating an intermediate parse tree or other persistent data structure. Other tools include Verilog, SystemVerilog and VHDL analyzers and elaborators, as well as a register transfer level (RTL) database. All are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and come with support and maintenance.

The entire Verific product line will be demonstrated during the 45th Design Automation Conference (DAC) in booth #655 June 9-12 at the Anaheim Convention Center in Anaheim, Calif.

The Concise Logic Optimization System, including Concise[tm] Optimizer and Concise[tm] Cells, is based on proprietary technology developed for digital logic optimization of complex circuits. It eliminates redundancies and inefficiencies difficult to visualize using other methodologies, reduces levels of logic throughout the circuit producing fewer nodes than conventional circuits and reduces tradeoffs between area, speed and power consumption.

“Concise Logic has the opportunity to change the way chips are optimized,” says Rob Dekker, founder and president of Verific. “It gives us great pleasure knowing that our Verilog Netlist Only Parser serves as the front end to this exciting new toolset.”

About Verific Design Automation
Verific Design Automation, with offices in Kolkata, India, and Alameda, Calif., is a leading provider of Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 30,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com.

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