Jasper Design Automation, the leader in successful deployment of production proven formal verification solutions, announced a major new release of its flagship formal verification solution: JasperGold® Verification System and JasperGold® Express version 5.0. This major release delivers three times (3X) greater proof capacity for superior formal verification performance enabled by two times (2X) the reduction in memory requirement, ten times (10X) faster core engines and powerful patented formal technology. Featuring new core engines, JasperGold v5.0 delivers dramatic improvements in both interactivity and tunneling performance.
With its recently announced automated proof accelerators, JasperGold can validate complex design behaviors that include FIFOs, memories, caches and multiple clock domains. Aimed at system architects, logic designers, verification engineers and silicon bring-up teams designing complex system chips, JasperGold v5.0 can be used to successfully prove protocols and executable specs; to design, explore and debug RTL; to ensure correctness of block-level functionality; and to conduct fast silicon validation and debug.
Developed using valuable feedback from its industry-leading customers, JasperGold v5.0 now delivers 3X higher proof capacity for tackling highly complex system-on-chip (SOC) designs. JasperGold’s higher proof capacity, with 2X memory reduction and 10X faster core engines, empower users to work on even larger designs and/or properties and achieve full proofs.
Enabled by a rich patent portfolio, JasperGold v5.0 also delivers improved interactivity that shortens debug time. With on-the-fly addition of constraints and the ability to rapidly generate new waveforms, JasperGold v5.0 delivers a superior debugging experience. The improved tunneling performance allows automatic analysis of the state space as well as interactive analysis by the user. And, with Solaris10 64-bit support, JasperGold now completes its full support for both 32-bit and 64-bit platforms, including Linux.
“From architecture to silicon, JasperGold v5.0 unleashes the power of formal verification for highly complex SoC design,” said Claudionor Coelho, vice president of engineering. “Now, users both familiar and unfamiliar with formal technology can successfully use it to validate architecture implementation, prove interface protocols, explore logic behavior, verify RTL functionality and performance, as well as validate silicon. By decreasing the design verification burden throughout the chip development flow, JasperGold v5.0 will help users gain greater design confidence, reduce risk, improve schedule predictability and boost design quality.”
JasperGold Verification System and JasperGold Express are currently being used worldwide by industry-leaders in communications, computing, consumer electronics, networking, processor and wireless design.
Pricing and Availability
JasperGold Verification System and JasperGold Express v5.0 are currently available. For complete product and pricing details, please call +1.650.966.0245.
Visit Jasper at DAC, booth #2346 – Register for a Demo Suite Appointment
Learn about Formal Verification Unleashed[TM] – an advanced verification methodology supported by best-in-class formal verification solutions, to exhaustively verify complex designs at any stage in the design flow, from architecture-level down to first silicon – at the 45th Annual Design Automation Conference (DAC). Look for Jasper at booth #2346 from June 8th to the 12th, 2008. To book an appointment, please call +1.650.966.0200. Demonstrations of the latest release of JasperGold Verification System, JasperGold Express and GamePlan Verification Planner will be available.
About Jasper Design Automation
Jasper Design Automation’s production proven formal verification solutions are used by logic designers, verification engineers and silicon bring-up teams to design, explore and debug RTL, to ensure correctness of block-level functionality and for rapid silicon validation and debug. JasperGold® Verification System delivers complete “deep formal” systematic verification, ensuring correctness of critical design features without any testbench development. JasperGold Express, a “light formal” solution, complements simulation by accelerating bug-hunting and coverage attainment.
Jasper Design Automation, the Jasper Design Automation logo, JasperGold, Formal Testplanner, GamePlan, Proof Accelerators, Lossless Abstractions, Formal Scoreboard, and Design Tunneling are trademarks or registered trademarks of Jasper Design Automation, Inc.