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OCP-IP Publishes Network on Chip Architectures Survey

Posted by Ken Cheung in Networking,Research on Tuesday, May 13, 2008

OCP-IP announced the availability of a white paper discussing a survey of Network-on-chip (NoC) proposals. NoCs replace dedicated, design-specific wires with scalable, general purpose, multi-hop networks. NoCs can provide separation between computation and communications, serve as a platform for test, and support IP reuse increasing engineering productivity and decreasing time to market. This paper gives an overview of the state-of-the-art regarding network-on-chip proposals.

The survey contains sections on NoC Architecture Comparison, Comparison Criteria, NoC Evaluation Methods, and NoC Router Implementation. NoC Architecture Comparison discusses switching policy, topology, routing, quality-of-service, as well as testing and fault tolerance. NoC Evaluation Methods covers evaluation metrics and example test cases. Router Implementation discusses router parameters, minimum latency, area and operating frequency.

This paper cites numerous examples from literature selected to highlight the contemporary approaches and reported implementation results.

A copy of the survey can be downloaded

Work on the survey of NoCs paper was completed by Tampere University of Technology and the OCP-IP NoC Benchmarking Group.

About OCP-IP
The OCP International Partnership Association, Inc. (OCP-IP), formed in 2001, promotes and supports the Open Core Protocol (OCP) as the complete socket standard ensuring rapid creation and integration of interoperable virtual components. OCP-IP’s Governing Steering Committee participants include: Nokia (NYSE: NOK), Sonics Inc., Synopsys (SNPS), Texas Instruments (NYSE: TXN), and Toshiba Semiconductor Group (including Toshiba America TAEC). OCP-IP is a non-profit corporation delivering the first fully supported, openly licensed, core-centric protocol comprehensively fulfilling system-level integration requirements. The OCP facilitates IP core reusability and reduces design time, risk, and manufacturing costs for SoC designs.

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