Design Automation Conference Features 29 Programs, Panels

The 45th Design Automation Conference (DAC) will include 29 Technical Program and Pavilion panels over a four-day period, covering a variety of topics and trends related to the design of chips and embedded software. DAC will be held June 8-13, 2008 at the Anaheim Convention Center in Anaheim, Calif.

“This year’s panel line-up is especially strong and diverse,” says Panel Chair Sachin Sapatnekar of the University of Minnesota. “The Panel Committee worked exceptionally hard this year to bring attendees the experts on the latest trends, the new technologies and the latest industry debates. I encourage everyone attending DAC to join the panel discussions.”

Nine panels in the Technical Program, offered from Tuesday, June 10, to Thursday, June 12, will tackle the most pressing challenges, including working with multicore architectures, electronic system level (ESL) design and wireless, this year’s DAC theme. Other subjects include verification, thermal, design for manufacturability (DFM) and custom design and synthesis.

One panel titled, “Electronics and Politics: What the Industry Needs from the Incoming U.S. Administration,” Tuesday from 10:30 a.m. to noon, will ask participants and attendees to consider the most important initiatives for the upcoming election.

Attendees will see familiar favorites among the 20 Pavilion Panels in Booth #364 on the DAC exhibit floor. Kicking off the program Monday is “Gary Smith on EDA: Trends” and “What’s Hot at DAC.” The Student Design Contest Award Presentation will be held Monday as well. Another favorite — Hogan’s Heroes — to be held Wednesday will attempt to answer, “Behavioral Synthesis: Is that Light at the end of the Tunnel or an Oncoming Train?” Thursday’s program includes “A Conversation with the 2008 Marie R. Pistilli Woman in EDA Award Winner.”

Monday Pavilion panel sessions include “EDA Heritage Series: Maxwell’s Legacy” and “Next-Generation Data Centers: Environmentally Green, Financially Green.” A panel of tech-savvy Java high school students will define cool in current devices and what they want in the future, in “Today’s Consumers: High Schoolers Spec Your Next Product.” Also to be held Monday is “Will 22 nanometer be Our Catch-22?”

Pavilion panels Tuesday are “45 nanometer: Collaborate, Aggregate, Differentiate” and “EDA: A View from Sand Hill Road.” Also planned for Tuesday are “Multiprocessor SoCs: The Next Generation,” “IP Selection: The Good, The Bad and The Ugly” and “EDA Globalization: Third World or New World?” Tuesday’s discussions continue with “Quality Versus Time to Market: The Unmentionable Tradeoff” and “SOI (silicon on insulator): Fact, Fiction or Future?”

Pavilion panel sessions Wednesday will be “Advanced Low-Power Techniques: Is Your Design Method too Powerful” and “DFM Design Rules: Worth The Effort?” “Designing the New-Generation Wireless Platform: Lesson from iPhone and Android” and “What’s Holding Back Analog Design Automation?” also are planned for Wednesday.

The Pavilion Panel Program concludes Thursday with “Your Functional Verification Roadmap: OVM, VMM or Roll Your Own?”

Visit the DAC Web site for the compete listing of panels, dates and times of each, along with a description of the topic, moderator and panelists.

This committee is headed by Panel Chair Sachin Sapatnekar of the University of Minnesota. Volunteer Panel Committee members are: Dave Reed of Blaze DFM Inc.; Andreas Kuehlmann at Cadence Design Systems Inc.; Tiffany Sparks at Chartered Semiconductor Manufacturing; Eshel Haritan of CoWare Inc.; Kevin Silver of Denali Software Inc.; Ruchir Puri from IBM; and Yatin Trivedi from Magma Design Automation Inc.

Also, Juan C. Rey from Mentor Graphics Corporation; Dave Kelf, of Sigmatix Inc.; Hiroyuki Yagi at STARC; Rich Goldman of Synopsys Inc.; Steve Leibson from Tensilica Inc.; Nagaraj NS of Texas Instruments; and Sabina Burns of Virage Logic Corporation.

Registration
To register for DAC, call 1-800-321-4573 in the U.S. to request registration materials. The advance conference registration discount deadline is May 19, 2008.

About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for Electronic Design Automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,500 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight is its Exhibition and Suite area with approximately 250 of the leading and emerging EDA, silicon and IP providers. The conference is sponsored by the Association for Computing Machinery’s Special Interest Group on Design Automation (ACM/SIGDA), the Circuits and Systems Society and Council on Electronic Design Automation of the Institute of Electrical and Electronics Engineers (IEEE/CASS/CEDA) and the Electronic Design Automation Consortium (EDA Consortium).