Jasper Design Automation Receives 7th Formal Verification Patent

Jasper Design Automation, provider of advanced formal verification solutions, announced a growing portfolio of innovative formal technology patents to help its worldwide customer base manage dramatically increasing SoC design complexity. The company is investing heavily in formal technology research and development (R&D). As a result of its aggressive and innovative R&D efforts, Jasper was granted its seventh patent by the U.S. Patent and Trademark Office.

Jasper’s strong portfolio of patents include:

  • Patent 7237208 – Managing Formal Verification Complexity Of Designs With Datapaths. This patent is instrumental in fast, high level proofs with data transport end to end properties. It creates a unique benefit for JasperGold, unparalleled proof convergence, and is also used in JasperGold Proof Accelerators. This approach has since been used successfully and further tuned in cooperation with multiple customers.
  • Patent 7020856- Method For Verifying Properties Of A Circuit Model. This patent covers advanced design space tunneling algorithm aspects. Using a proprietary, systematic process for formal, this patent enables Jasper’s formal technology to reach proof convergence for complex designs, and allows white box discovery of design elements, such as datapath.
  • Patent 7065726 – System And Method For Guiding And Optimizing Formal Verification For A Circuit Design. This second design state tunneling patent covers additional technologies and applications, focusing on user interface aspects. The advanced debugging GUI aspect contributes to Jasper’s industry leadership in deploying design space tunneling with debugging in the field.
  • Patent 7137078 – Trace Based Method For Design Navigation. This patent allows white box debugging, filtering large amounts of design information to pinpoint the root cause of design errors, and tracing the root cause to the specific line of RTL. Since 2003, Jasper’s intuitive user interface and trace generation for debug has been tuned for formal verification.
  • Patent 7159198 – System And Method For Identifying Design Efficiency And Effectiveness Parameters For Verifying Properties Of A Circuit Model. This patent covers a seminal form of formal prediction as well a form of ‘on-the-fly’ formal prediction during the design tunneling process. The concept is the basis of the Jasper Formal Predictor[tm].
  • Patent 6611947 – Method For Determining The Functional Equivalence Between Two Circuit Models In A Distributed Computing Environment; Plus Patent 6993730 – Method For Rapidly Determining The Functional Equivalence Between Two Circuit Models. These two patents cover verification as manifested in equivalence checking.

The patents that have been issued to date have enabled Jasper’s customers to tackle highly complex designs without the usual capacity or performance constraints once associated with formal verification; to reach proof convergence for complex designs with large sequential depth due to counters and datapath elements; and to conduct early formal prediction with unique design space tunneling technology.

“At Jasper, we have been working aggressively to address the next generation of SoC design challenges – from the architecture level down to first silicon – by innovating and applying advanced formal technologies to solve key problems at every stage of the design flow,” said Rajeev Ranjan, Jasper’s chief technology officer. “Our commitment to the advancement of formal technology has made it possible for us to amass a growing portfolio of issued and pending patents. Customers applying our Formal Technology Unleashed tell us that they can now ensure higher design quality and greater design confidence.”

To learn more about Jasper and its Formal Technology Unleashed[tm] – an advanced verification methodology supported by patented, best-in-class formal verification solutions to comprehensively verify complex designs at any stage in the design flow, from architecture to first silicon – please visit Jasper’s booth #2346 at the 45th annual Design Automation Conference (DAC) in Anaheim, California, June 8th to the 12th, 2008. Please call +1.650.966.0200 for further details.

About Jasper Design Automation
Jasper Design Automation’s production proven formal verification solutions are used by logic designers, verification engineers and silicon bring-up teams to design, explore and debug RTL, to ensure correctness of block-level functionality and for rapid post-silicon validation and debug. JasperGold® Verification System delivers complete “deep formal” systematic verification, ensuring correctness of critical design features without any testbench development. JasperGold Express, a “light formal” solution, complements simulation by accelerating bug-hunting and coverage attainment.

Jasper Design Automation, the Jasper Design Automation logo, JasperGold, Formal Testplanner, GamePlan, Proof Accelerators, Lossless Abstractions, Formal Scoreboard, and Design Tunneling are trademarks or registered trademarks of Jasper Design Automation, Inc.