Genesys Testware, Inc., a leading supplier of yield, quality and cost optimization tools for nanometer ICs, announced the addition of Design For Leakage Test (DFLT) features to its hierarchical scan test tool, HiertestMaker[TM]. Reducing power dissipation and energy use is the biggest challenge facing IC designers today. Leakage is the largest contributor to IC power and energy for designs manufactured using advanced manufacturing processes (minimum feature size of 90nm or less).
Leading IC designers use power gating (addition of power controllers, power switches and isolation gates) to reduce leakage. However certain faults in power controllers, power switches and isolation gates cannot be detected by traditional Design for Test (DFT) schemes and Automatic Test Pattern Generation (ATPG) software. This problem can be eliminated using existing ATPG software by adding DFLT circuitry around power controllers, power switches and isolation gates. DFLT circuitry can now be automatically added to any IC design using the hierarchical scan test tool HiertestMakerTM. Unlike competing IEEE 1500 based bottom-up design methodologies, this approach does not require changes to the efficient top-down design flows in use today and require less area overhead.
“IC developers can now obtain a comprehensive leakage test methodology for their low power designs at low cost,” said Vinod Sutrave, President of Network Silicon, Inc., a leading IC design services company. “Moreover, it works seamlessly with scan ATPG tools from Synopsys, Mentor, Cadence and Magma,” Vinod added.
“IC developers eliminate a coverage hole in addition to lowering scan test application and generation time using our boundary scan based hierarchical test tool,” said Bejoy Oomman, President of Genesys Testware. “Moreover this capability comes at no additional cost in design time or chip area,” Bejoy added.
The DFLT feature of HiertestMakerTM is available at no additional cost to existing users of HiertestMaker[TM] now. HiertestMaker[TM] starts at $60,000 for a single year subscription.
This new tool will be demonstrated during the upcoming 45th Design Automation Conference that will be held from June 9-12, 2008 at the Anaheim Convention Center, Anaheim, California in Exhibitor Booth #1536.
More information: Genesys Testware