Apache Design Offers Chip Package Co-Design Methodology Webinar

Apache Design Solutions, the technology leader in power, noise, and reliability (PNR) signoff for chip, package, and system designs, announced that the company will present an online technical webinar entitled “Chip-Package Co-Design: Applying Chip Power Model in System Power Integrity Analysis.” Apache will detail the methodology used for integrated chip-package co-design based on a Chip Power Model (CPM), as well as design examples to demonstrate application and results.

The live webinar will be broadcast via TechOnLine:

Thursday, May 8, 2008
11:00 a.m. PDT, 2:00 p.m. EDT

Power, noise, and reliability are critical design challenges for system engineers today, Shrinking geometry, increasing functionality, higher input-output (I/O) signaling speed, low-power / low-leakage design techniques, and advanced packaging technologies such as system-in-package (SiP) exacerbate management of power, noise, and reliability challenges. The webinar will discuss co-design methodology and CPM, an accurate model of the die’s power delivery network (PDN) switching noise. It will demonstrate how CPM can be used during early stage prototyping to optimize package/board designs, resulting in the most cost effective products. Highlights include:

  • Chip power integrity and its impact of package and board
  • Early system prototyping with accurate chip power model
  • Methodology for IC-aware package analysis and optimization

About Apache Design Solutions
Apache delivers the leading power signoff solution adopted by 80% of the top IDM, fabless semiconductor, and foundries and a complete platform for silicon integrity of low-power, high-performance system-on-a-chip (SoC) designs. Apache’s innovative platform considers multiple noise sources that impact the design—such as power, signal, package / system IO, substrate, and temperature—and enables designers to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon and/or system. Apache’s vendor-neutral solution supports any industry-standard physical design flow and is certified by TSMC and Common Platform Reference Flows. Apache is a global company with R&D centers and direct sales / support offices worldwide.

Apache Design Solutions, NSPICE, RedHawk, PakSi-E, PakSi-TM, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.