STARC STARCAD-CEL 2.0 Design Flow Features Atrenta Tools

Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, announced the integration of its SpyGlass®, SpyGlass-Constraints, SpyGlass-DFT, SpyGlass-Power, and 1Team®-Implement products into the latest production flow from the Semiconductor Technology Academic Research Center (STARC). Called STARCAD-CEL Version 2.0, the new production flow supports RTL analysis as well as chip implementation, offering a comprehensive solution for early constraints analysis and management, design-for-test (DFT), low power design, and design feasibility analysis. The Atrenta products were proven effective in the STARCAD-CEL reference flows.

STARC engineers conducted an exhaustive evaluation of the Atrenta products on advanced designs that included RTL test cases ranging from basic functionality to complex multi-million gate designs. The SpyGlass tool suite provides comprehensive design analysis for Early Design Closure and minimizes design implementation risks.

“In our evaluations, SpyGlass-Constraints impressed us with its ability to detect and correct critical issues with design constraints including verification of false and multi-cycle paths,” said Nobuyuki Nishiguchi, vice president and general manager at STARC. “By integrating the SpyGlass-DFT solution into the production flow, we have provided our customers with a design for test solution that combines accurate test coverage at the RTL-level, interactive debugging of testability issues early in the design cycle, and automated repair of the RTL code.”

One of the primary focal points for STARC is low power design. With respect to the SpyGlass-Power product Nishiguchi-san added, “We validated the accuracy of Atrenta’s RTL power estimation, the effectiveness of its power reduction technology, and the ability to verify the correctness of the power infrastructure (level-shifters, isolation logic, and power connections).”

The 1Team-Implement solution enables early feasibility analysis of the design specification and enables chip architects to assess the impact of architectural tradeoffs. The product’s analysis capabilities enable IP designers and RTL designers to rapidly identify, debug and fix potential timing, power, area and congestion issues.

“Our evaluation of RTL prototyping capabilities using 1Team-Implement covered several designs. We were able to correctly identify congested blocks early in the design cycle. We were also able to reduce the floor plan iterations from 5 to 2 by using 1Team-Implement’s solution on our productivity benchmark,” said Nobuyuki Nishiguchi. “Our evaluation showed that 1Team-Implement not only delivered good quality floor plans, but also demonstrated excellent correlation with the congestion analysis engines of the P&R tools in the reference flows.”

“We are pleased with STARC’s broad endorsement of Atrenta’s Early Design Closure solutions. Their detailed analysis has proven Atrenta’s ability to reduce design iterations and improve overall design quality,” said Mike Gianfagna, vice president of marketing at Atrenta. “With the STARCAD-CEL Version 2.0 production flow, customers now have access to the most advanced Early Design Closure tools, resulting in more predictable implementation schedules and better design performance.”

About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to optimize their designs early in the RTL phase for linting, clock domain crossings (CDC), power estimation and reduction, design for test (DFT), constraints generation and validation including timing exceptions, and RTL prototyping. Atrenta optimized RTL delivers up to 30% efficiency gains in chip integration, implementation and verification phases. Atrenta has over 140 customers, including the world’s top 10 semiconductor companies.

The Semiconductor Technology Academic Research Center (STARC) was established in December 1995 with investment from Japan’s leading semiconductor suppliers to reinforce semiconductor design capability. Since its inception, STARC has been conducting joint research with universities and the semiconductor industry to strengthen the bases of research in the field of semiconductor technology at domestic universities. The outcomes of these activities are utilized industry-wide in Japan through the transfer of technologies to investing companies to help their businesses, the documenting of technical standards, and the licensing of technologies to partner companies for commercialization. Headquartered in Shin Yokohama, Japan, STARC is co-funded by 11 member companies including Fujitsu Microelectronics Limited, Matsushita Electric Industrial Co., Ltd., NEC Electronics Corporation, Oki Electric Industry Co., Ltd., Renesas Technology Corporation, Rohm Co., Ltd., Sanyo Semiconductor Co., Ltd., Seiko Epson Corporation, Sharp Corporation, Sony Corporation, and Toshiba Corporation.

Atrenta, the Atrenta logo, SpyGlass, 1Team, and Early Design Closure are registered trademarks of Atrenta Inc.