Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that Time To Market, Inc. (TTM), a leading ASIC design house, was able to detect hot spots and optimize yields for a complex 65-nanometer design using a holistic design-for-manufacturability flow from Cadence that includes the Cadence® SoC Encounter(tm) XL system and the Cadence Litho Physical Analyzer. The proof-point project provided TTM with state-of-the-art DFM experience and allowed the company to move to Cadence model-based DFM solutions for ongoing 65-nanometer and below designs.
“Time To Market, Inc. is focused on providing customers first-pass working silicon that meets both performance and yield goals,” said Venkata Simhadri, president and CEO of TTM. “Cadence’s holistic, integrated DFM solution helped us to achieve these critical goals by addressing manufacturing issues during the design phase and improving productivity and manufacturability. We used the Cadence SoC Encounter XL and Litho Physical Analyzer to optimize a complex 65-nanometer chip design and prevent lithographic errors from occurring in chip manufacturing, for faster time to production and an improved yield for our customer.”
“Time To Market’s primary differentiation is providing accelerated time to market for nanometer designs and mitigating customers’ risk,” said Nitin Deo, DFM group marketing director at Cadence Design Systems. “By using our model-based DFM analysis, TTM validated its customers’ 65-nanometer networking SoC in record time, working the design into a highly manufacturable state in a very short time. Customers are finding that addressing manufacturability issues during the design stage can reduce schedule variation and yield risk at advanced nodes.”
TTM chose Cadence due to the quick and reliable results obtained with its model-based DFM products, which can improve yield on aggressive designs at 65 nanometers and below. TTM was impressed with the integration of the Cadence DFM solution and Cadence digital implementation technologies — which help to speed overall design cycle. This approach aligns very closely with TTM’s holistic design strategy and allows the company to tackle the design and manufacturing challenges at 65nm and below with Cadence DFM solutions.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,300 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence and Encounter are registered trademarks, and the Cadence logo is a trademark, of Cadence Design Systems, Inc.