Actel to Discuss Power Efficiency at Embedded Systems Conference

Posted by EDA Geek News Staff in Events, Training, FPGAs on Monday, April 14, 2008

Speakers from Actel Corporation will address the growing need for power efficiency at the chip and system levels at Embedded Systems Conference Silicon Valley, being held April 14 - 18 in San Jose, California at the McEnery Convention Center. Topics will include methods to minimize power consumption for portable applications; embedded design using an FPGA-optimized ARM Cortex-M1 processor; and design techniques for power-efficient motor control. In their private meeting center, Booth #106, Actel will end the programmable logic industry’s low-power leadership debate, comparing the company’s award-winning 5 microWatt IGLOO FPGAs to competitive CPLD and FPGA offerings.

Design Techniques for Power-Efficient Motor Control
Ravi Pragasam, Actel
Tuesday, April 15, 12:30 - 2:00 pm

Embedded Design with FPGAs and ARM Cortex-M1
Mike Thompson, Actel
Dominic Pajak, ARM
Jean Labrosse, Micrium
Tuesday, April 15, 2:30 - 4:00 pm

FPGAs and ARM - Minimizing Power for Portable Applications
Hezi Saar, Actel
Dominic Pajak, ARM
Wednesday, April 16, 10:30 am - 12:00 pm

About Embedded Systems Conference Silicon Valley
Embedded Systems Conference Silicon Valley delivers a comprehensive technical program focusing on critical topics that affect today’s designs and help solve engineering issues. More than 350 leading vendors will exhibit the newest product applications.

About Actel
Attacking power consumption from both the chip and the system levels, Actel Corporation’s innovative FPGAs and programmable system chip solutions enable power-efficient design. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655.

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