Seiko NPC Tapes Out with Cadence Encounter Test Architect, RTL Compiler

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that Seiko NPC Corporation successfully taped out a complex audio DSP design using Cadence® Encounter® Test Architect and Encounter RTL Compiler global synthesis technologies. Using the industry award-winning Encounter Test Architect and Cadence Encounter RTL Compiler, Seiko NPC designers were able to automatically insert, synthesize and validate the DFT infrastructure of a leading-edge design, greatly accelerating design time, reducing risk and enabling a higher degree of architectural exploration.

“The joint use of Encounter Test Architect and Encounter RTL Compiler global synthesis enabled our design team to hand-off a fully testable audio DSP design, including a complex clock architecture, high-speed multiplier and many memories, in less time, allowing us to meet our schedule, quality and cost goals,” said Akehito Gunji, EDA engineering manager at Seiko NPC. “Encounter Test Architect and Encounter RTL Compiler enabled greater optimization, providing a back-to-back logic and test synthesis environment.”

Seiko NPC’s experience underscores that a highly integrated design environment creates multiple points of benefit, often capitalizing on the benefits achieved at previous design stages. For instance, by applying Encounter RTL Compiler physical technology, Seiko NPC was able to achieve better timing convergence during physical implementation. In addition, an Encounter Test Architect XOR compression macro was inserted during synthesis enabling significant test data volume reduction which led to reduced manufacturing costs. Also, Seiko NPC was able to rigorously test embedded memories in the design using the Memory Built-In Self Test (MBIST) capability in Encounter Test Architect.

“Using Cadence Encounter Test Architect and Encounter RTL Compiler with global synthesis, customers such as Seiko NPC are able to experience significant benefits in automation, risk reduction, design time and design optimization,” said Nimish Modi, corporate vice president of the Cadence Front End Design Group. “This is a powerful proof of the benefits of a highly integrated design environment.”

Encounter Test Architect is a complete solution to insert, synthesize and validate a full-chip DFT infrastructure. These basic methodologies include scan insertion using Encounter RTL Compiler with global synthesis technology; top-level I/O test structures, including IEEE 1149.1 boundary scan; on-chip compression with multiple input signature register (MISR) architecture or exclusive-or (XOR)—based architectures; and memory BIST solutions.

Encounter Test Architect and Encounter RTL Compiler with global synthesis technology are key components of the Cadence Logic Design Team Solution and digital implementation user segments. They are both available in L, XL, and GXL offerings.

From Encounter RTL Compiler 7.2 version, all the Encounter Test Architect based original DFT capabilities have been integrated into the Encounter RTL Compiler platform. Using this new Encounter RTL Compiler based logic-test synthesis platform, the users will be able to run through the logic and test synthesis flow in one pass at ease. More developments are on the way to make this new logic-test synthesis platform stronger and easier to use.

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,300 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

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