Synplicity, Inc. (NASDAQ:SYNP), a leading supplier of innovative IC design and verification solutions, released its newest version of the company’s Synplify® DSP ESL synthesis software for ASIC and FPGA design. The Synplify DSP 3.6 software includes new enhancements to its architectural optimizations and DSP synthesis methodology, as well as new Intellectual Property (IP) blocks and capacity improvements that will benefit customers working on complex digital multimedia and wireless IC designs.
The Synplify DSP tool provides a unique ESL synthesis methodology that realizes significant productivity and portability advantages over traditional HDL design flows. System and algorithm designers quickly can capture complex algorithmic behavior using the Synplify DSP library which includes powerful modeling features such as vector arithmetic, fixed-point precision up to 128-bits, and a rich set of IP cores. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed-optimized RTL implementations from a single model. This eliminates the burden of hand coding functions and architectural optimizations, achieves significantly faster design capture, speeds time to market and enables rapid design exploration that results in improved quality and lower cost.
Synplicity has enhanced the optimization engine to recognize repeating patterns of operations in the design, and apply time-multiplexed scheduling to reduce the implementation area. This results in much lower area across a broader set of algorithm designs. This technique is ideal for designers working on applications such as wireless, radar, and digital video compression which typically require patterns that are highly replicated.
“Our architectural synthesis methodology will serve the needs of designers developing systems where parallelism and multiple sample rates are the design paradigm,” says Chris Eddington, Synplicity’s director of DSP marketing. “These include applications in wireless, radar and video compression, where multiple instances of IIR, FIR filter banks and multiple channels of any type of filter block are in use. Our architectural optimizations can reduce real estate by as much as 90 percent.”
New IP Cores
For digital multimedia and wireless applications, the Synplify DSP 3.6 software now includes Reed-Solomon Encoder and Reed-Solomon Decoder blocks. These functions provide burst error correction for a variety of modern communication standards used in broadband modems, digital video broadcast, storage, and military/aerospace communications. The Synplify DSP Reed Solomon cores are extremely flexible with a broad range of bitwidth, codeword, message size, erasure, and polynomial generator support. In addition, these cores benefit from the Synplify DSP architectural optimization methodology where tradeoffs between low-area or high-speed are automatically chosen based on the target technology and user constraints. This delivers better results than parameterized RTL cores and makes Synplify DSP IP cores very easy to use for both FPGA and ASIC technologies.
Improved saturation and rounding capabilities have also been added to the Synplify DSP 3.6 library. The tool offers a full range of rounding options across the entire library so users gain more flexibility in controlling the precision and stability of their algorithms.
To support customers implementing multi-FPGA designs, Synplicity has improved the capacity of the DSP synthesis optimization engine in the Synplify DSP 3.6 software. The tool now supports 10 times larger models and design complexity—ideal for military and aerospace applications where large FPGAs or multiple FPGAs are in use.
Synplicity®, Inc. (NASDAQ:SYNP) is a leading supplier of innovative IC design and verification solutions that serve a wide range of communications, military/aerospace, semiconductor, consumer, computer, and other electronic applications markets. Synplicity’s FPGA implementation tools provide outstanding performance, cost and time-to-market benefits by simplifying, improving and automating logic synthesis, physical synthesis, analysis and debug for programmable logic designs. Synplicity’s ESL synthesis solutions significantly improve productivity for DSP designs realized in ASIC and FPGA devices. The Confirma(tm) at-speed verification platform, comprising software tools and the HAPS(tm) family of prototyping systems, enables both comprehensive verification of ASIC, ASSP and SoC designs and software development prior to chip tapeout. Synplicity is the number one supplier of FPGA synthesis tools and its physical synthesis and ASIC verification technologies are the recipients of several prestigious industry awards. The company operates in more than 20 facilities worldwide and is headquartered in Sunnyvale, California.