Tensilica Xenergy Estimator Features New Graphical User Interface

Tensilica,® Inc. announced that it has added a new graphical user interface (GUI) to its popular Xenergy(tm) estimator, a unique energy estimator for both Xtensa® configurable processors and Diamond Standard processors. This “first of its kind” tool allows software developers to evaluate trade-offs, so their software can be optimized for power, and lets hardware designers optimize the design of Xtensa configurable processors for total energy consumption.

“Today, total energy consumption is a primary design consideration for both hardware designers and software developers in most market segments,” stated Steve Roddy, Tensilica’s vice president of marketing and business development. “Often, it isn’t intuitive which design decisions will have the biggest impact on overall energy consumption for a new SOC design. By using Xenergy, designers can quickly evaluate the trade-offs and know that they’ve picked the most energy efficient way to design new products.”

Xenergy for Optimized Processor Hardware Configuration
Configurable processor technology has long been known for its potential to accelerate performance. But tailoring a processor to a given task can also be used with energy minimization as a key consideration. Using Xenergy, hardware designers can drive Xtensa processor configuration choices to dramatically lower the total clock processor cycles required to perform a given functional workload, thereby reducing total energy consumed. Designers pick from a menu of different configuration options and add custom processor extensions to try to reduce total core power consumption.

The Xenergy energy estimator calculates total energy consumption for a specific software workload on a candidate processor configuration. Comparisons between candidate processors are graphically displayed. Output can be a simple text file or a colorful graph for easy evaluation.

Tests of processor configurations for common embedded processing kernels such as dot product, the Advanced Encryption Standard (AES) encryption, Viterbi decoding, and Fast Fourier Transform (FFT) show that the energy improvements from processor customization can range from 2x to 83x (all comparisons using common process, design flow and libraries).

Configuration   Dot Product AES Viterbi FFT
Baseline Xtensa K Cycles 12 283 280 326
  Energy (µJ) 3.3 61.1 65.7 56.6
Optimized Xtensa K Cycles 5.9 2.8 7.6 13.8
  Energy (µJ) 1.6 0.7 2.0 2.5
Energy Improvement   2x 82x 33x 22x

The Xenergy estimator can also be used to evaluate the power savings potential of different process technologies, instruction and data cache sizes, RAM and ROM sizes, and many other Xtensa processor configuration options.

Xenergy for Optimized Software Design
Even after a processor configuration is chosen, or after an SOC has been fabricated, software developers can also use the Xenergy estimator to fine tune their C code to reduce energy dissipation by the processor and its memories. For example, a developer might use the feedback provided by the Xenergy tool to decide to restructure the allocation of data structures in local and main memories to reduce memory and bus accesses, which will lower overall energy expenditures. The Xenergy estimator gives the software developer fast, visual feedback and pinpoints the code hot spots that are consuming the most processor cycles and generating the most memory accesses.

Xenergy, with its new graphical user interface, is shipping now as part of Tensilica’s Software Development Kit, which includes all software development tools, the instruction set simulator, and the Xtensa Xplorer(tm) design environment.

About Tensilica
Tensilica, Inc., is the recognized leader in configurable processor technology and has leveraged that technology to become the leading supplier of licensable controllers and DSP cores for mobile audio and video applications. Tensilica offers the broadest line of controller, CPU, network, and specialty DSP processors on the market today – including full software toolchain and modeling support – in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. The modern design behind all of Tensilica’s processor cores provide semiconductor companies and system OEMs with the lowest power, smallest area solutions for high-volume products including mobile phones and other consumer electronics, networking and telecommunications equipment, and computer peripherals.

Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc.