ViASIC Technology Reduces ASIC Tapeout to Two Weeks

ViASIC Inc., an electronic design automation (EDA) company that offers breakthrough tools, IP and services for reconfigurable semiconductor fabrics, announced its technology has achieved a significant, proven advancement in ASIC design – reducing the traditional eight-to-12-week turnaround time from “design freeze” to “silicon in hand” to two weeks.

Albuquerque, N.M.-based Sandia National Laboratories demonstrated this rapid turn-around for radiation-hardened (rad-hard) designs, using its ViArray trusted structured ASIC implementation platform based on ViASIC’s patented standard metal configurable fabric and Sandia’s radiation-hardened technology. ViASIC’s pre-defined and pre-characterized base platform lets manufacturing begin before design completion, and enables much earlier silicon availability. Using pre-qualified base arrays helps companies reduce non-recurring engineering (NRE) and development costs, and significantly improves time to market.

Applying ViASIC’s patented fabric to rad-hard integrated circuits allows transistors to be characterized before via layer configuration begins. Staged characterized wafers can be stored at the fab, because characterization of the base layer transistors is totally independent of the design process.

Mark Goode, president and chief executive officer at ViASIC, said, “As an early adopter of ViASIC’s via-configurable fabric, Sandia spearheaded the move to a two-week turnaround time for companies developing rad-hard military system applications. The rad-hard area long has needed this time-critical turnaround, and we are so pleased to enable another customer to capitalize on a fast turn for its market space.”

Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin company, for the U.S. Department of Energy’s National Nuclear Security Administration. With main facilities in Albuquerque, N.M., and Livermore, Calif., Sandia has major R&D responsibilities in national security, energy and environmental technologies, and economic competitiveness. Sandia’s ViArray trusted structured ASIC platform demonstrates electrical performance superior to that of FPGAs and approaching that of standard ASICs, and offers comparable computing and processing resources.

Kwok Kee (K.K.) Ma, manager of Advanced Microelectronics and Radiation Effects at Sandia National Laboratories said, “Our military system customers appreciate the value of moving from design to working prototype in just two weeks. We are pleased that by incorporating ViASIC’s technology into our trusted rad-hard foundry, we can offer our customers fast-turn, low NRE-cost ASICs for rad-hard applications.”

ViASIC and Sandia will participate in the 26th annual Hardened Electronics and Radiation Technology (HEART) Conference in Colorado Springs, Co., Mar. 31 – Apr. 4, 2008. Please visit ViASIC (Booth 12), and Sandia (Booth 5) to learn more about reducing turnaround time for rad-hard applications.

About ViASIC
ViASIC Inc. supplies proven electronic design automation (EDA) tools, IP and services that leverage reconfigurable semiconductor fabrics to slash mask costs by up to 95% compared to a standard ASIC design approach, and reduce both design time and risk. Its patent-pending solutions, both with and without SRAM, let ASSP providers, product designers, test chip designers and others in commercial and radiation-hardened applications start manufacturing before the design is fully completed, and debug silicon far earlier in the design flow, speeding time to market. Founded in 2000, ViASIC is headquartered in Durham N.C.

ViASIC is a registered trademark of ViASIC, Inc.