Rishiyur S. Nikhil, CTO of Bluespec(TM) Inc., developer of the only ESL synthesis for control logic and complex datapaths in chip design, will present “Bluespec: General-purpose High-Level Synthesis Using Parallel Atomic Transactions” at the Design Automation and Test in Europe (DATE) 08 workshop entitled “The New Wave of High-Level Synthesis.”
Dr. Nikhil will present during session 4, “The Future of High-Level Synthesis”, at 14:45-16:45 on Friday, March 14, in room 03 at the ICM in Munich, Germany.
Bluespec SystemVerilog (BSV) will be contrasted against traditional (C-based) high-level synthesis (HLS), which has narrow applicability to loop-and-array algorithms (such as FFTs and FIR filters) because of C’s sequential semantics. Dr. Nikhil will highlight BSV’s underlying technology, atomic transactions, and how BSV applies across the full spectrum of data- and control-oriented blocks found in modern SoCs for modeling, verification and implementation.
A core technology for many next generation multi-core processors and concurrent software languages, atomic transactions are the highest known level of specification of complex concurrent behavior. Atomic transactions attack the fundamental issue that makes hardware and concurrent software so error-prone, brittle, complex and costly to develop and verify – managing concurrent accesses to shared resources.
Bluespec Inc. manufactures industry standards-based Electronic Design Automation (EDA) toolsets that significantly raise the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. The toolsets, the only ones focused on control and complex datapaths, allow ASIC and FPGA designers to reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found by calling (781) 250-2200.
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