Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, announced an addition to its SpyGlass® design analysis platform – SpyGlass-DFT DSM. The new SpyGlass-DFT DSM solution is the industry’s first tool which will accelerate design turnaround times by identifying timing closure issues caused by at-speed testing – early at RTL.
The new product introduces advanced timing closure analysis and RTL testability improvement for deep submicron (DSM) defects associated with at-speed testing. It provides accurate RTL fault coverage estimation for transition delay testing, together with diagnostics for low fault coverage, early in the design flow, to achieve high test quality with minimum design iterations.
“At 90nm and below, most of our semiconductor customers are challenged with low at-speed coverage, even in cases with high stuck-at coverage,” said Kiran Vittal, product marketing director for test and clocks products at Atrenta. “Our new design-for-test product is yet another industry first in testability analysis and RTL fault coverage estimation that addresses these deep submicron challenges. The SpyGlass-DFT DSM product is the only tool that works at RTL to identify timing closure issues caused by at-speed test logic and helps designers to minimize design iterations and meet their design schedules.”
Atrenta is unveiling the new SpyGlass-DFT DSM product at this year’s Design, Automation & Test in Europe (DATE) conference.
The test clocks in traditional stuck-at testing are designed to run on test equipment at frequencies lower than the system speed. At-speed testing requires test clocks to be generated at the system speed and these clocks are often shared with functional clocks from a phase locked loop (PLL) clock source. The additional test clocking circuitry affects functional clock skew and thus the timing closure of the design. SpyGlass-DFT DSM is designed to specifically address the problems associated with timing closure due to at-speed DFT.
At-speed tests often result in lower than required fault coverage, even with full-scan and high (>99%) stuck-at coverage. Identifying reasons for low at-speed coverage at the ATPG stage is too late to make changes to the design and affects schedules significantly. SpyGlass-DFT DSM identifies causes of low at-speed coverage at RTL and helps achieve quick turnaround times for today’s aggressive design schedules and time-to-market challenges.
Pricing and Availability
The SpyGlass-DFT DSM product was developed in consultation with several Atrenta customers in Europe, India, Japan, Korea and the U.S. The product will be available in SpyGlass version 4.0, scheduled for release in April 2008. The U.S. list price is $75,000 for a one-year time based license.
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to optimize their designs early in the RTL phase for linting, clock domain crossings (CDC), power estimation and reduction, design for test (DFT), constraints generation and validation including timing exceptions, and RTL prototyping. Atrenta optimized RTL delivers up to 30% efficiency gains in chip integration, implementation and verification phases. Atrenta has over 140 customers, including the world’s top 10 semiconductor companies.
Atrenta, the Atrenta logo, SpyGlass, 1Team, Early Design Closure are registered trademarks of Atrenta Inc.