Aldec Debuts ALINT Stand Alone Verilog Design Rule Checker

Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced the world-wide release of ALINT(TM), a stand-alone Verilog design rule checker that complies with the second edition of the STARC “RTL Design Style Guide for Verilog HDL.” Initially released in Japan, ALINT reduces the risk of developing complex multi-million gate ASICs by resolving structural, coding and consistency problems early in the design cycle. It detects design issues at the point of creation. ALINT offers a comprehensive solution for clock & reset analysis, detecting potential clock domain crossing (CDC) issues.

“ALINT is one of the tools that support STARC RTL Design Style Guide for Verilog HDL 2nd Edition, which is widely accepted in Japan,” stated Mr. Yoshiharu Furui, Senior Manager, Design Standard Group of STARC. He expects that “by using tools such as ALINT, designers will develop higher quality SOC designs and decrease their overall time to market.”

Main ALINT Capabilities
ALINT is a static Verilog design rule checker that includes support for rules that operate at several levels of abstraction: Verilog Language, Synthesizable Verilog RTL Subset, Block-Level Netlist and Chip-Level Netlist.

Verilog Language Rules enable detection of errors related to the use of undesired data types, bit-width mismatches, missing size/base specification for constants and parameters. These rules also detect typical errors with logic designs including bitwise and conditional expressions, style, and naming conventions.

Synthesizable Verilog RTL Subset Rules are automatically applied to the Verilog code and ALINT performs checks against the use of improper constructs for synthesis: unspecified conditional statements, resource sharing in the synthesized netlist, simulation/synthesis mismatches and inaccuracy with multiple assignments to the same signal.

Block-Level Netlist Rules – Built-in synthesis emulation automatically recognizes typical hardware elements from RTL code and builds a internal netlist model that allows detection of unwanted latches, flip-flops with fixed values on the inputs, detection of problems with asynchronous controls of inferred flip-flops and issues with multiply-driven nets.

Chip-Level Netlist Rules monitor a typical DFT problem, such as influence of global clock signals on non-clock ports, uncontrollability of clock/reset/enable pins of storage elements, unwanted asynchronous feedbacks and interconnections typically leading to DFT and ATPG tools malfunctions.

Cross-Probing of Warning Messages
ALINT stores all violations to a highly optimized database and then displays all violations in the console window. Double-clicking on the violation reported in the console window cross-probes directly to the line of Verilog source code creating the violation. Post-linting analysis can be performed on any violations stored in the database, eliminating the need to run ALINT again in order to recall violations collected in other parts of a project.

Configuration Management
The ALINT engine provides a flexible configuration mechanism. ALINT provides a preinstalled set of STARC rules. Rules can be combined together in different ways to form rule sets and policies that are treated by ALINT as a single object. The rule, rule set and policy properties can be easily configured, providing additional flexibility in design analysis.

ALINT is available today and includes an HDL Editor, STARC based design rules, and lint engine. The product is sold directly from Aldec and its authorized world-wide distributors.

Semiconductor Technology Academic Research Center (STARC) was established in December 1995 with investment from Japan’s leading semiconductor suppliers to reinforce semiconductor design capability. Since its inception, STARC has been conducting joint research with universities and the semiconductor industry to strengthen the bases of research in the field of semiconductor technology at domestic universities. The outcomes of these activities have now been utilized industry-wide in Japan through the transfer of technologies to investing companies to help their businesses, the documenting of technical standards and the licensing of technologies to partner companies for commercialization. STARC is co-funded by 11 member companies including Fujitsu Limited, Matsushita Electric Industrial Co., Ltd., NEC Electronics Corporation, Oki Electric Industry Co., Ltd., Renesas Technology Corporation, Rohm Co., Ltd., Sanyo Semiconductor Co., Ltd., Seiko Epson Corporation, Sharp Corporation, Sony Corporation, and Toshiba Corporation.

About Aldec
Aldec, Inc. established in 1984, is committed to delivering best value-in-class products to government, military, aerospace, telecommunications, automotive and industrial customers. Aldec offers a patented technology suite of robust EDA verification products including: design entry, software simulators, co-simulation, linting software, prototyping, hardware accelerators, hardware emulators, co-verification solutions, IP Cores, DO-254 compliance solutions and engineering services. Continuous innovation, superior product quality and total commitment to customer service comprise the foundation of Aldec’s corporate mission.

ALINT is a trademark of Aldec, Inc.