Archive for February 2008

Synopsys IC Compiler 2007.12 Features Concurrent Hierarchical Design

Posted by EDA Geek News Staff in EDA Tools on Friday, February 29, 2008

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, announced the availability of the industry's first concurrent hierarchical design system as part of the IC Compiler 2007.12 release. As designers migrate to smaller geometries, on-chip integration increases and design sizes mushroom, making hierarchical design almost mandatory. Current-generation design tools rely on a "plan-then-implement" flow which begins to break down in the face of these large designs, which often include multiple modes and multiple voltage domains. The IC Compiler 2007.12 release transcends these flows by enabling a concurrent methodology where planning occurs in tandem with implementation, delivering faster time to tapeout. The 2007.12 release also introduces new advances in clock tree synthesis technology that improves clock skew and lowers power dissipation. The new release directly boosts designer productivity by providing a 30 percent reduction in total run time.

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Mistral Customizes Software, Hardware Solutions for TI' OMAP35x

Posted by EDA Geek News Staff in EDA Tools on Friday, February 29, 2008

Furthering its role as a catalyst between product developers and technology companies, Mistral, a leading product realization company specializing in real-time embedded solutions, announced that it is now geared up to provide customized hardware and software solutions for the high-performance OMAP35x(TM) platform from Texas Instruments (TI).

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AMD Develops Chip with Extreme Ultra-Violet Lithography

Posted by EDA Geek News Staff in Research on Friday, February 29, 2008

AMD (NYSE: AMD), working together with its research partner, IBM, announced it has produced a working test chip utilizing Extreme Ultra-Violet (EUV) lithography for the critical first layer of metal connections across the entire chip. Previous projects utilizing EUV to produce working chip components were only "narrow field", covering just a very small portion of the design. The work of AMD, IBM, and their partners at the UAlbany NanoCollege's Albany NanoTech Complex, will be presented by Dr. Bruno La Fontaine of AMD at the premier lithography conference in the industry on Tuesday. The paper will show successful integration of "full-field" EUV lithography into the fabrication process across an entire 22 mm x 33 mm AMD 45 nm node test chip.

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STMicroelectronics Announces STM8 8-bit Microcontroller Platform

Posted by EDA Geek News Staff in Microcontrollers on Friday, February 29, 2008

STMicroelectronics (NYSE: STM), one of the world's leading semiconductor manufacturers and a leader in ICs for automotive applications, has unveiled details of a new 8-bit microcontroller platform designed to offer outstanding levels of performance and cost-effectiveness in a wide range of applications. Implemented around a high-performance 8-bit core and a state-of-the-art set of peripherals, the STM8 platform will be manufactured using an ST-proprietary 130nm embedded non-volatile memory technology.

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Synopsys Proteus Pipeline Technology Reduces Design-to-Mask Cycle Time

Posted by EDA Geek News Staff in EDA Tools on Friday, February 29, 2008

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, announced the capability to pipeline key manufacturing applications. This new Proteus Pipeline Technology provides a fully pipelined tapeout flow for maximum CPU utilization and is a major departure from serial manufacturing flows, in which a complete post-optical proximity correction (OPC) database must be available before the latter applications can be initiated. By deploying this capability across its portfolio of proven manufacturing tools, Synopsys provides customers with increased hardware efficiency, enabling significant reductions in both CPU memory consumption and manufacturing turnaround time.

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European Consortium to Develop 0.5 TeraHertz Silicon Transistor

Posted by EDA Geek News Staff in Research on Friday, February 29, 2008

A powerful European consortium held the kick-off meeting of the EU-funded project labeled DOTFIVE and titled "Towards 0.5 TeraHertz Silicon/Germanium Heterojunction Bipolar technology (SiGe HBT)." Led by STMicroelectronics, the consortium is setting out to develop advanced silicon-based bipolar transistors with a maximum operating frequency of 0.5 THz (0.5 TeraHertz or 500 GigaHz) needed for future millimeter wave and terahertz communication, radar, imaging and sensing applications. The three-year project is worth Euros 14.75 million withEuros 9.7 million European Commission funding, making it the largest (More than Moore) nanoelectronics project under EU Framework Programme 7.

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