Lattice 17K LUT LatticeXP2-17 FPGA Enters Volume Production

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced that the 17K LUT LatticeXP2-17 device, one of five members of its third-generation non-volatile LatticeXP2(tm) FPGA family, has been fully qualified and released to volume production. Designed using the industry’s most advanced non-volatile FPGA technology, a 90nm embedded Flash process manufactured on 300mm wafers, the LatticeXP2 devices provide the “instant-on” and reduced footprint benefits of earlier Lattice non-volatile devices, while also enhancing design security, RAM back-up and live update capabilities.

The production release of the LatticeXP2-17 comes approximately nine months following the initial product announcement. This rapid time to production demonstrates Lattice’s ongoing commitment to leadership in the non-volatile FPGA segment, and to delivering “More of the Best” to its customers. With over twenty years of experience in non-volatile programmable logic, Lattice’s market experience has shown repeatedly that as the premium charged for a non-volatile solution is reduced at each new process node, significantly more users will take advantage of the benefits of non-volatility.

“The market response to our LatticeXP2 FPGAs has been enthusiastic, and we are gratified by our customers’ appreciation for our unique value proposition,” said Stan Kopec, Lattice corporate vice president of marketing. “Only our unique flexiFLASH(tm) non-volatile plus SRAM architecture, with on-chip Flash memory, provides all the benefits of a true non-volatile logic technology.”

flexiFLASH Architecture
The LatticeXP2 family consists of five members, with logic capacities from 5K to 40K 4-input Look Up Tables (LUTs). I/O counts across the family range from 86 to 540 in space-saving package configurations as small as an 8mm x 8mm chip-scale BGA package (csBGA). Embedded block memory provides up to 885Kbits in 18Kbit dual port blocks. For small scratch pad memories, LUTs can also be converted into small, distributed memory blocks. To support increasingly common DSP applications, up to 8 sysDSP(tm) blocks provide hardwired high-performance pipelined multiply and accumulate functions. The devices have up to four Phase Locked Loops (PLLs) that allow designers to align and synthesize clocks as required in their designs.

Flash memory blocks are embedded within LatticeXP2 FPGAs to store the device configuration, providing a true single chip solution that Lattice calls the flexiFLASH architecture. At power up or on user command, the data stored in the Flash memory is transferred into SRAM cells that control the configuration of the device. This transfer is done in a massively parallel fashion, enabling the device logic to be available in approximately 1mS, well ahead of the other devices in the system and much faster than SRAM-based FPGAs that use external boot PROMs, regardless of whether they are provisioned separately on-board or stacked in the same package. This instant-on capability is critical for many system functions such as power up sequencing, address decoding and reset logic.

By keeping the configuration bitstream on-chip, the LatticeXP2 devices are also inherently more secure than alternative multiple device or multi-chip module solutions. This security is enhanced by configuration read-back protection modes. A 64-bit erase/program lock protects against accidental or unauthorized device programming. A one time programmable (OTP) mode is provided for ultimate protection against unauthorized programming. Optional 128-bit AES encryption can be used to secure programming data being passed into the device.

Design Tools and Intellectual Property
Design support for the LatticeXP2 family is provided by the latest generation of Lattice’s ispLEVER® design tool suite, version 7.0 with Service Pack 2. In addition to providing design support for the LatticeXP2 family, the version 7.0 release provides major general enhancements including substantial speed and utilization improvements for all Lattice FPGA families, a greatly enhanced Power Calculator module and the Reveal(tm) design analysis tool with the industry’s most advanced logic analysis triggering capabilities. Customers can also choose from an extensive library of IP cores, shortening the design cycle and accelerating time to market.

Pricing and Availability
The LatticeXP2-17 is available now in two package options (256 ftBGA and 484 fpBGA). Prices for the LatticeXP2-17 start at $9.95 for delivery in the 2nd half of 2008 in 100,000 piece quantities.

About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays ( FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products. Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile, and low-cost FPGAs. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispLEVER, LatticeXP2, flexiFLASH, sysDSP, Reveal and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.