EVE will host its Billion Cycle Challenge seminar series for hardware designers, verification engineers, electronic systems level (ESL) architects, R&D managers, firmware and embedded software managers this month in Paris, London and Munich, Germany.
The seminar will be held February 26 in Paris:
HOTEL MERCURE RONCERAY – 10 Boulevard Montmartre, 75009 Paris
and moves to Swindon, U.K., February 27:
Express by Holiday Inn Swindon City Centre
The series concludes in Munich, Germany, February 28:
NH München-Dornach Messe- und Kongresshotel
The Paris seminar will be conducted almost entirely in French, while the other two will be conducted in English.
Presented by EVE and co-sponsored by Synopsys Inc., the half-day seminar promotes a new methodology to address hardware/software co-verification of complex systems on Chip (SoCs) and application specific integrated circuits (ASICs).
Using examples from real projects, it will illustrate a solution to the Billion Cycle Challenge already in use by leading semiconductor companies.
EVE is the worldwide leader in hardware/software co-verification solutions, including hardware description language (HDL) acceleration and extremely fast emulation. EVE products significantly shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products also work in conjunction with popular Verilog, SystemVerilog, and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics. Its United States headquarters are in Santa Clara, Calif.