At the International Solid-State Circuits Conference (ISSCC) Texas Instruments Incorporated (TI) (NYSE: TXN) disclosed process and design advancements enabling the first 45 nanometer (nm) 3.5G baseband and multimedia processor addressing critical power challenges in the wireless market. TI’s expertise in chip technologies are increasing performance while lowering power requirements in this custom solution which the company recently began sampling in fourth quarter 2007 to a wireless customer. TI’s 45nm process incorporates various technology advancements and design techniques along with new SmartReflex(TM) 2 power and performance management technologies. With these advancements, wireless customers will be able to deliver smaller, sleeker devices with advanced multimedia functionality, realizing a 55 percent performance increase and 63 percent power reduction versus the 65nm process.
Leveraging the 45nm process
In a paper presented today, Dr. Uming Ko, TI Senior Fellow and director of TI’s Wireless Chip Technology Center, described the new device that is based upon TI’s low-power 45nm process. The process is designed to address the specific needs of the portable device market, initially mobile handsets, which uses immersion lithography tools and ultra-low K dielectrics to double the number of chips produced on each silicon wafer, while giving its customers a performance boost over the current 65nm low power process. The performance enhancement is achieved through a number of proprietary techniques including strained silicon to further reduce leakage in the 45nm process.
TI’s first 45nm wireless digital and analog design platform leverages and integrates hundreds of millions of transistors in a 12mm x 12mm package. The platform includes a high-throughput communication and high-performance multimedia applications engine based on an ARM11, high performance TMS320C55x(TM) digital signal processor (DSP), and an image signal processor, bringing a consumer-electronics quality experience to mobile handsets that work across multiple wireless standards. A number of analog components are also integrated, including an RF Codec.
“Today’s announcement demonstrates TI’s commitment to delivering high-performance, low power wireless solutions that help handset manufacturers better address advancements in the wireless market,” said Jeff Bellay, vice president, Wireless Advanced Technology. “The ability to dramatically impact the power and performance of silicon allows our customers to deliver next-generation handsets that feature truly impressive multimedia capabilities using minimal power.”
The dramatic performance boost achieved at the 45nm process node is ideal to meet the increasing demands of the mobile multimedia environment. Customers can design and deliver handsets that will enhance the user experience enabling high-definition (HD) video playback and record, running simultaneous applications such as a game with 3-D graphics in parallel to a video conference between the players. The ability to reduce power allows for more advanced features and applications to be included in handset designs, as well as increased video playback, talk and stand-by time.
Dramatic power reductions with SmartReflex 2 technologies
Overall power management is particularly critical to the wireless market, and the challenges faced as communications and computing continue to converge on mobile devices, directly impacting battery life. TI remains at the forefront of the market in delivering technology innovation to allow its customers to deliver high performing, more power-efficient products, including process technology and design techniques that are integrated across the company’s broad portfolio of analog and DSP products.
One example of this is TI’s SmartReflex technologies that were introduced in TI’s 90-nm process that include a range of hardware and software techniques to address power management at the system level across an entire design. In TI’s enhanced SmartReflex 2 technologies, new capabilities are introduced including TI’s patented Adaptive Body Bias (ABB), Retention ‘Til Access (RTA) memory and SmartReflex PriMer tools. The SmartReflex 2 technologies allow the 45-nm process to deliver intelligent chip performance and power reduction.
ABB is an intelligent adaptive technology that allows for automatic, dynamic voltage adjustment to best derive the power and performance from the processor to meet the needs of the mobile device without additional wafer complexities and cost. This technology addresses the issue of supporting additional voltage which requires more processing steps and is typically linked to higher manufacturing cost. ABB consists of forward body-bias (FBB) for performance boost and reverse body-bias (RBB) for power reduction. The ABB approach enables an optimal balance of power and performance with circuit techniques alone, eliminating the need for additional logic transistors with different threshold voltages.
Special leakage management functions such as RTA provide the ability to switch to low-power modes in response to active processes. With TI’s RTA technology, the memory is segmented, lowering voltage while continuing to retain memory data. This gives the overall system more power to efficiently run other power-hungry applications and reduce power drain.
In addition to hardware advancements, TI is introducing its SmartReflex PriMer power management tools. SmartReflex PriMer tools are a series of automated tools for a system-on-chip (SOC) design that reduce time to market by helping to automate register transfer language (RTL) generation, ensuring that it is correct by construction. This gives TI customers a simpler way to implement SmartReflex power and performance management techniques into future product generations.
TI is focused on delivering flexible external and internal manufacturing for high volume production of customer designs on the advanced processes they require. Fabricated using a low-power digital and analog design platform and 45-nm process technology, TI met its commitment to the market by shipping the first samples of a 45-nm wireless SoC solution in the fourth quarter 2007 and expects fully qualified production in 2008 on 300 millimeter (mm) wafers.