Auspy Development, Inc, the leading independent supplier of partitioning tools for SoC prototyping, and GiDEL, a leading supplier of reconfigurable systems for SoC verification and complex algorithm acceleration, announced the establishment of a technology collaboration. Auspy and GiDEL will work closely to deliver full support of Auspy’s ACE partitioning tool suite for the full range PROC systems used in the verification and debug of SoC designs.
Auspy’s ACE partitioner provides fully automatic and semi-automatic modes of operation, and takes into consideration full timing characteristics of the single board and multiple board architectures within the PROC family of systems from GiDEL. Of particular value is the support for hierarchy within the partitioning tool for the unique architecture of the PROC_SoC systems. The PROC_SoC can have up to ten, dual FPGA boards, with over 700 user’s defined any FPGA to any FPGA connections in 118 pin blocks. The partitioning tool will allow users to interactively guide the FPGA interconnection, or develop an interconnection map for the system’s bus and cable types of high speed interconnections. The software will also enable users to take advantage of the LVDS support in the Stratix devices.
“We are delighted to be working closely with GiDEL to augment their SoC verification solution,” said Auspy President, Nang-Ping Chen. “The opportunity to support GiDEL’s large and growing based of SoC design teams is a tremendously exciting opportunity.”
The PROC_SoC(TM) and PROC board-level reconfigurable systems feature advanced Altera Stratix® II and Stratix III FPGAs that can be configured to emulate and verify complex SoC designs across a broad spectrum of applications over 100 million ASIC gates in complexity.
“Providing a hierarchical partitioning tool will provide great productivity enhancement for our customers to verify their SoC designs on our PROC platforms,” added Reuven Weintraub, President and CTO of GiDEL. “Auspy has been maturing and polishing ACE for over a decade to become the leading independent partitioning product on the market.”
Joint Demonstrations at DesignCon 2008 and DVCon 2008
Auspy and GiDEL invite attendees to the DesignCon 2008 and DVCon 2008 conferences to a detailed product demonstration of the combined solution. Stop by the GiDEL booth # 520 at DesignCon 2008, Santa Clara Convention Center, Santa Clara, California, February 5 and 6, and booth #802 at DVCon, Doubletree Hotel, San Jose, February 19 and 20.
GiDEL Ltd. is a successful, profitable and innovative company which was founded in 1993. GiDEL has become one of the market leaders as a company that continuously provides cutting-edge reconfigurable technology utilizing FPGAs. GiDEL sees it’s customers as partners and uses its vast experience at the project-level and FPGA design to focus on its customers’ projects’ success. Customers in semiconductor, consumer product, communications, machine vision, medical imaging, and military/aerospace markets purchase the PROC family of reconfigurable PROCessors (1) for SoC and ASIC verification, (2) as COTS (Commercial Off-The-Shelf) acquisition and accelerator boards, and (3) to validate complex algorithms. For more information, contact GiDEL in North America at 408-969-0389, or worldwide at +972 4 610 2505.
About Auspy Development, Inc.
Auspy Development Inc. is an EDA company specializing in next-generation multiple-FPGA partitioning solutions that cost-effectively automate the implementation of ASIC prototypes. Auspy licenses its products to commercial prototyping platform vendors. More than 100 copies of software have been sold worldwide through OEM partners and used successfully to partition complex ASIC designs with up to 40 million gates. Auspy is very proud of its commitment to customers and partners, and sells and supports commercial or custom-built prototyping platforms together with its OEM partners and distributors. For more information, contact Auspy at 408-252-5813.
GiDEL, PROCWizard, PROCStarIII are registered trademarks and trademarks of GiDEL Ltd.