Xilinx Inc. (Nasdaq: XLNX), the world’s leading supplier of programmable logic solutions, outlined plans for participation at next week’s DesignCon 2008 conference, including an FPGA industry business forum panel, DesignVision awards, high-speed serial backplane conference session and a Virtex(TM)-5 FPGA enabled cell broadband demonstration.
Xilinx at DesignCon
Tuesday, February 5
10:15-11:45 a.m. Business Forum Panel
“Executive Views on the Turbulent FPGA Landscape”
Xilinx panelist Bruce Tally, vice president and general manager of the Design Software Division, joins a panel discussion examining key FPGA industry trends, including vendor independence, tool interoperability, and next generation technology.
12:00 p.m. DesignVision Awards
Xilinx(R) ISE(TM) software and MOST(R) NIC LogiCORE(TM) IP Solution are DesignVision Awards finalists. Winners will be announced in the main theater.
Xilinx ISE design environment is designed to address today’s leading design challenges including timing closure, productivity and power. 9.1i optimizes the unique ExpressFabric(TM) technology of the latest 65nm Virtex(TM)-5 FPGAs, providing an average of 30 percent faster performance than competing solutions. For power-sensitive applications, ISE 9.1i software also reduces dynamic power by an average of 10 percent. For more information about the ISE 9.1i software suite, http://www.xilinx.com/products/design_resources/design_tool/index.htm
Xilinx MOST NIC LogiCORE IP Solution, in conjunction with the Xilinx Automotive (XA) solution and embedded processing, allows designers to leverage the MOST network by providing a higher level of customization in a scalable and flexible design solution. A complete hardware and software solution is realized when the core is used in conjunction with Xilinx MicroBlaze(TM) soft processor solution, drivers, and MOCEAN Network Services. For more information about the MOST NIC LogiCORE IP, http://www.xilinx.com/automotive
Thursday, February 7
10:40-11:20 a.m. Conference Session 7-THA3
“A Design of Experiments for Gigabit Serial Backplane Channels”
Jack Carrel, system I/O specialist at Xilinx, Bill Dempsey, president at Red Wire Enterprises, and Mike Resso, signal integrity expert at Agilent Technologies, will examine the challenges facing today’s high-speed serial backplane designers. Tradeoffs between signal integrity performance, cost, and reliability must be made to achieve the proper architecture for a robust physical-layer channel. The right combination of connectors, dielectric materials, and topology must be used to accomplish this engineering task. In this session, presenters will provide an in-depth look at the design of experiments using combinations of three high-speed connectors, three dielectric materials, and three channel lengths. Results of data analyzed with a 12-port vector network analyzer will be presented in time domain, frequency domain, and eye diagram domain.
IBM demonstrates Cell Broadband Engine(TM) interfacing with Virtex-5 FPGA
IBM System & Technology Group/IBM Research demonstrates a Cell Broadband Engine(TM) (Cell BE) connected to a Virtex-5 FPGA via FlexIO(TM) interface. This is the first and fastest coherent/non-coherent interface between the Cell BE processor and an FPGA. The Cell BE processor interfaces to RocketIO(TM) GTP transceivers at 3 Gbps resulting in a transfer bandwidth of 3 Gbps per FlexIO byte lane. This architecture can enhance the use of Cell BE processors for custom I/O interfacing, offloading specific tasks or interconnecting multiple processors. Visit Rambus/IBM at booth #205 for a demo and more information.
About DesignCon 2008
DesignCon is the essential design engineering event addressing the challenges facing these communities and providing the solutions attendees can implement immediately in their designs.
Xilinx is the worldwide leader in complete programmable logic solutions.