Femto Forum Launches Program for Femtocell Network Integration
The Femto Forum, the independent industry association that supports femtocell deployment worldwide, has launched a programme to help harmonise the integration of femtocells into mobile core networks. Operator demand to launch femtocells quickly has led to the development of many different methods for integrating potentially millions of femtocells into the network core. Although this is not holding up the commercial deployment of femtocells, this programme will help unite these different approaches in the longer term and set the stage for the development of future standards.
STMicroelectronics Creates 24-bit Audio DAC with Playback Time Extender
STMicroelectronics (NYSE: STM) announced a very high performance 24-bit audio DAC (digital to analog converter) that is intended for the mobile music market and provides 103dB signal-to-noise ratio through the whole audio path, while also embedding the company’s innovative PTE(TM) Playback Time Extender processing scheme to minimize power consumption. The single-chip STw5210 audio solution also integrates power management circuitry to simplify system design and enable direct connection to the battery, and is available in small TFBGA and VFQFPN packages and, soon, in a tiny 2.6 x 2.6mm WLCSP.
Technosoft Debuts MxK28335 Motor Control Kits with Floating Point DSC
Technosoft announces the new MxK28335 DSC Motor Control Kits family based on the TMS320F28335 floating-point digital signal controller (DSC). From basic starter kits to most sophisticated professional kits with complete source code application examples and function libraries, these kits offer a wide range of excellent tools for the design of DSP-based motor control applications. They have a modular structure; you can easily upgrade from a simpler kit to a more powerful one, as your project’s complexity requires it, by adding new software / hardware modules.
SYSGO PikeOS Conforms to ARINC 653 Part 3 Standard with Skysoft AVT
SYSGO announced the full compliance of their PikeOS ARINC 653 Personality to the ARINC 653 Part 3 standard. The tests have been accomplished with Skysoft’s verification tools (AVT), which is the result of a tight cooperation between the two companies.
SYSGO Rolls Out PikeOS Board Support Package for Kontron AM4100 AMC
SYSGO announced the availability of a PikeOS Board Support Package for Kontron’s AM4100, an AdvancedMC (AMC) board using the MPC8641D dual-core processor based on the latest generation of Freescale’s E600 core. The PikeOS BSP has been developed to be used in a multi-application system for an avionics equipment to be certified to DO178B.
Inphi DDR3 Clock Reference Board Clocks in at 800 MHz
Inphi® Corporation announced its ground-breaking DDR3 Clock Reference Board (CRB), which performs beyond JEDEC DDR3-1600 specifications, achieving clock speeds of 800 MHz. Designed specifically for high performance RDIMM testing, the DDR3 CRB enables major memory module and system designers to validate DDR3 RDIMMs and simulate system-level functionality effectively and efficiently, providing a comprehensive validation tool for DDR3 Register/PLLs. The DDR3 CRB is part of Inphi’s market-leading ExacTik(tm) product family.
Lattice Unveils AEC-Q100 Certified Power Manager II Products
Lattice Semiconductor Corporation (NASDAQ: LSCC) announced that automotive versions of its second generation Power Manager II product family, the popular ispPAC-POWR1014 and ispPAC-POWR1014A, have been characterized and qualified to meet the certification requirements of the AEC-Q100 standard as defined by the Automotive Electronics Council (AEC). The Power Manager II family is a functional superset of Lattice’s award winning ispPAC® Power Manager programmable mixed signal devices, which provide a complete power management solution for a printed circuit board (PCB) through an optimized set of programmable digital and analog functions. Lattice AEC-Q100 qualified devices are designated as Lattice Automotive, or “LA.” These devices join the previously announced LA-MachXO Crossover Programmable Logic Devices, the LA-ispMACH® 4000V and LA-ispMACH 4000Z CPLDs in Lattice’s growing automotive product portfolio. Production quantities of the new devices will be available later in Q1 2008, and Lattice can provide standard PPAP (Production Part Approval Process) documentation to automotive customers who require it.
Synopsys DesignWare DDR Protocol Controller IP Integrates with Arteris NoC
Arteris, the leading provider of Network-on-chip (NoC) solutions and Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, announced the integration of Synopsys’ DesignWare® DDR Protocol Controller IP and the Arteris NoC solution for complex system-on-chips (SoCs). This combination delivers reliable, high-speed, on-chip connectivity with low latency to external DDR2 and DDR3 SDRAM memory for advanced systems.
AdaCore Introduces GNATcheck Coding Standard Verification Tool
AdaCore, provider of the highest quality Ada tools and support services, announced the availability of GNATcheck, an integrated coding standard verification tool within the GNAT Pro development environment. GNATcheck meets the growing need for automated verification in safety-critical avionics systems, particularly those systems that need to satisfy the DO-178B standard. Developed by RTCA and EUROCAE, DO-178B defines the guidelines for development of aviation software in both the US and Europe and is being increasingly adopted by other related sectors, such as air traffic control and military applications.
Magma Rolls Out Talus QDRC for Physical Design Verification
Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, announced Talus® QDRC, a physical design verification product that improves productivity and time to market for 65- and 45/40-nanometer (nm) designs by identifying and correcting design rule violations during implementation. Unlike prevailing DRC methods that require streaming data from an implementation database – resulting in missed errors that require design rework, lengthening the design cycle of today’s complex devices significantly – Talus QDRC decreases overall design costs by addressing Design Rule Check (DRC) problems before they delay design tapeout. Talus QDRC is deploying today on 65- and 45/40-nm designs.
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