Magma Design Automation Inc. (NASDAQ: LAVA), Mentor Graphics Corporation (NASDAQ: MENT) and Synopsys, Inc. (NASDAQ: SNPS) announced that the three companies are now delivering low power EDA tools based on the Accellera-developed Unified Power Format standard, UPF 1.0. This includes a broad range of implementation and verification products from the three companies. This new UPF product support further enhances key low power capabilities in the companies’ tools while expanding industry interoperability, especially when compared to other available options.
The three companies will present at an Accellera UPF Update during the System Design Forum 2008 at the EDS Fair in Yokohama, Japan on Jan. 25. This session will focus on the benefits of UPF for low power flows and tool interoperability.
The UPF standard enables end users to create a consistent, succinct, unified description of the low power design intent for use by EDA tools offering advanced features for design and verification of today’s low power integrated circuits (ICs). This benefits designers in two key ways. First, UPF supports integrated low power design flows from RTL to silicon, enabling consistent low power design intent to be applied and used throughout the flow. Second, the UPF standard enables interoperability, so tools from over two- thirds of the EDA marketplace can be used together utilizing the same low power methodology and design specifications.
“It is good news that such a broad selection of tools is now supporting UPF,” said Hartmut Hiller, senior director, design methodology at Infineon Technologies. “This milestone allows us to begin our UPF evaluations and hopefully the fast application for our world class low-power product portfolio.”
“Power management is a key challenge for all leading-edge chip designs, whether they are targeted for wireless consumer devices or large compute servers plugged into the wall,” said Kam Kittrell, general manager of Magma’s Design Implementation Business Unit. “It’s not sufficient for each EDA tool to handle these challenges individually-all the tools that make up the design environment, including implementation, verification and analysis, must do so in a consistent manner. UPF enables tool interoperability, allowing effective specification and power management across the entire design tool spectrum, and brings tremendous value to the design community.”
“UPF came about from the low power design industry’s challenge to Accellera to define an open, inclusive low power design format. Mentor Graphics and the EDA industry have embraced the UPF standard and are now delivering on the promise of design tool interoperability in low power design flows and the portability of low power design data,” said Stephen Bailey, functional verification product marketing manager at Mentor Graphics. “The level of interest in UPF-based solutions portend a bright future for this new standard.”
“The UPF Standard represents a win/win/win for industry interoperability and cooperation,” said Rich Goldman, vice president of Strategic Market Development at Synopsys. “Design teams win from better low power flows and greater tool interoperability, EDA vendors win from a consistent Accellera/IEEE standard and the world wins from chips that consume far less energy. Through low power design, electrical engineers will be a major contributing factor in helping the world resolve its climate change challenges, and the EDA industry will help them get there.”
A number of EDA tools from a broad range of companies support UPF today. More specific information about product support for UPF can be obtained from each company. An overview of current support is available at: http://www.unifiedpowerformat.com/images/UPF_Solutions_Guide.pdf
UPF is the electronics industry standard for capturing and using low power design intent for design automation. UPF was ratified by the Accellera standards organization in February 2007 and now forms the basis of the IEEE standards project 1801, the standard for low power IC design and verification. The most recent UPF specification from Accellera can be found at http://www.accellera.org/apps/group_public/documents.php?wg_abbrev=p1801
If you are interested in the IEEE-P1801 working group standardizing the low power format under the IEEE, visit: http://www.accellera.org/activities/p1801_upf/
Magma’s software for designing integrated circuits (ICs) is used to create complex, high-performance chips required in cellular telephones, electronic games, WiFi, MP3 players, DVD/digital video, networking, automotive electronics and other electronic applications. Magma’s EDA software for IC implementation, analysis, physical verification, circuit simulation and characterization is recognized as embodying the best in semiconductor technology, enabling the world’s top chip companies to “Design Ahead of the Curve”(tm) while reducing design time and costs. Magma is headquartered in San Jose, Calif., with offices around the world. Magma’s stock trades on Nasdaq under the ticker symbol LAVA.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $825 million and employs approximately 4,300 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Synopsys, Inc. (NASDAQ: SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The Company delivers technology-leading system and semiconductor design and verification platforms, IC manufacturing and yield optimization solutions, semiconductor intellectual property and design services to the global electronics market. These solutions enable the development and production of complex integrated circuits and electronic systems. Through its comprehensive solutions, Synopsys addresses the key challenges designers and manufacturers face today, including power management, accelerated time to yield and system-to-silicon verification. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia.
Synopsys is a registered trademark of Synopsys, Inc.