DVCon Reveals Technical Program for 2008

The Design and Verification Conference (DVCon) announced the 2008 technical program for the annual conference, which will be held February 19-21, 2008 at the DoubleTree Hotel in San Jose, California. In addition to continuing its tradition of providing educational and practical material that can be implemented in today’s designs, this year the conference will pay special attention to the verification of low power designs.

“This year at DVCon, attendees can look for fresh approaches to design and verification problems,” stated Steve Bailey, general chair of DVCon 2008. “In particular, the growing interest in functional verification as a critical discipline for electronic systems design and development will be addressed with sessions on low power design verification, verification methods and formal verification.” To read a complete letter from the general chair, please visit http://www.dvcon.org/html/about.html.

Highlights of DVCon 2008
This year’s conference includes a total of 10 in-depth technical paper sessions, presenting a wide range of topics including verification methodology, formal verification and functional coverage, as well as verification of low-power, multi-clock and analog/mixed-signal systems. There are also several sessions on applications of SystemVerilog and SystemC for verification, and an invited session on advances in research from both industry and academia. As always, the first day of the program includes five sponsored half-day tutorials, providing in-depth looks at a variety of state-of-the-art verification topics. These sessions were garnered from a total of 110 submitted abstracts that were reviewed in detail by the technical program committee.

Two highlights of the conference will take place on Wednesday, February 19: the keynote address by Dr. Wally Rhines, CEO and Chairman of the Board for Mentor Graphics Corp., and the annual “Troublemaker’s Panel” organized and moderated by John Cooley.

Dr. Rhines will be speaking about the complexity challenges in functional verification which are forcing designers to adopt new approaches, as well as the impact these changes will have on engineers. He will address the question, “Will the next advances in verification require engineers to relearn much of their approach to design, as they did when schematic capture gave way to hardware description languages, or will these changes be more evolutionary in nature?”

DVCon is also the venue that has become well-known for John Cooley’s unconventional “Troublemaker’s” panel where prominent industry figures are put in the hot seat with unedited questions supplied by the 25,000 members of ESNUG.

On Thursday, attendees will also have the opportunity to attend a panel event called “Driving Design Verification Results: Formal Verification Comes of Age.” Speakers will address strategies for eliminating redundant verification efforts, increasing verification productivity and reducing interoperability problems. Panelists will include representatives from Cadence Design Systems, Inc.; IBM, Corp.; Intel, Corp.; Jasper Design Automation, Inc.; and Mentor Graphics, Corp.

In addition to a great technical program, DVCon also has increased the size of the exhibit floor to accommodate more vendors this year. Hours for the exhibits are Tuesday from 4:30 p.m. to 7:30 p.m. and Wednesday from 4:30 .pm. to 7:30 p.m. It is complimentary registration to attend the exhibits and the pass includes access to the keynote as well as the Troublemakers panel.

About DVCon
DVCon is sponsored by Accellera, an industry consortium dedicated to the development and standardization of design and verification languages.