Mentor Graphics Corporation (Nasdaq: MENT) announced new technology in its Olympus-SoC(TM) place and route product that dramatically accelerates signal integrity (SI) closure and improves the reliability of manufactured silicon. The Multi-Corner, Multi-Mode (MCMM) capability of Olympus’ Static Timing Analysis (STA) engine concurrently computes delay shift and glitch for any number of mode/corner scenarios in a single pass. MCMM analysis enables customers to address reliability issues such as crosstalk delay, glitch, power, and electromigration while reducing the time to achieve design closure. The Olympus-SoC product’s detailed routing and optimization engines have been enhanced to help eliminate SI violations concurrently over all variation scenarios.
Customers designing at 65/45nm are experiencing a significant increase in SI related timing violations due to increasing dominance of lateral wire capacitance. An explosion in the number of mode and corner scenarios that must be addressed exacerbates the problem, significantly increasing the time to design closure. Current solutions are severely limited due to inability of the core STA engines to represent more than a single mode/corner combination for SI analysis. This severely hampers design teams who are forced to run several iterations with a lot of manual intervention.
Mentor’s Place and Route division has invented a breakthrough technique to concurrently compute and maintain mode/corner-specific delay shift, glitch, power, and electromigration (EM) data in a single analysis run. The solution includes several enabling technologies:
- Per clock, per corner, and per mode timing window computation
- Fast incremental SI updates over all mode/corners concurrently during implementation
- Routing techniques such as SI driven track assignment, wire spreading, and track reordering
- SI bottleneck identification for directed concurrent delta-delay, delta-slew, glitch optimization
“Multi-mode multi-corner SI closure is a latent design issue that critically impacts design performance and schedules,” said Senthil Krishnasamy, Physical Design Director at AMD. “Mentor’s new MMMC SI optimization technology addresses this issue comprehensively, and we are very impressed with the quality of results and the reduced time to design closure. Olympus-SoC MMMC SI optimization is now a standard part of our design flow.”
“AMD is designing some of the world’s most complex chips and we are very happy to partner with them in solving 65/45nm design issues,” said Pravin Madhani, general manager, Place and Route Division, Mentor Graphics Corporation. “Other solutions, including signoff quality timing and SI engines, are critically handicapped because they were designed to handle SI analysis for only one corner at a time. Olympus-SoC’s MCMM SI capability addresses a major unmet need in the design community.”
About the Olympus-SoC Product
The Olympus-SoC product is the next generation place and route system that concurrently addresses variations in lithography, process corners and design modes. It is built on the Pinnacle(TM) product, Mentor’s customer proven design-for-variability physical implementation solution. Technology highlights include lithography-driven detailed router, embedded signoff quality timing engine, and an adaptive variability engine, in addition to an open architecture and ultra-compact database that can handle extremely large capacities.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $825 million and employs approximately 4,300 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Mentor Graphics is a registered trademark and Pinnacle and Olympus-SoC are trademarks of Mentor Graphics Corporation.