Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that fundamental new technologies have been integrated into the Cadence® Incisive® Enterprise verification family that enable engineering teams to address increasingly complex chip design for products such as multi-mode cell phones, gaming consoles and HD-DVD players.
Incisive technologies now offer support for the newly developed Open Verification Methodology (OVM), a powerful new aspect-oriented generation engine, and the second generation of Cadence transaction-based acceleration (TBA) with native support of multiple testbench languages and numerous productivity enhancements. The new aspect-oriented generation engine leverages aspect-oriented programming (AOP) architected testbenches to improve performance and scalability. These major enhancements to the Cadence Incisive Specman® Testbench, Incisive Enterprise Simulator, and the Incisive Palladium® and Xtreme® hardware acceleration/emulation systems are in addition to numerous productivity enhancements.
New Aspect-Oriented Generation Engine
Incisive Enterprise Simulator and Incisive Specman Testbench feature a new aspect-oriented generation engine targeted for advanced verification specialists executing complex, aspect-oriented sequences against large designs. The new engine increases performance by nearly five times for e-based verification environments.
“The latest aspect-oriented generation technology within the Cadence advanced verification offering illustrates their continuing effort to provide verification technology that will keep pace with our design complexity,” said Thomas Kraus, verification manager at Siemens A&D. “By combining improved performance, built-in planning and management and system-level scalability, we’re ready to verify our next generation of designs with confidence.”
Support for Open Verification Methodology
As design complexity escalates, building and debugging verification testbenches becomes increasingly difficult. The mixed-language Incisive Enterprise Simulator now supports the Open Verification Methodology and its underlying class library, which significantly reduces the time it takes to create SystemVerilog verification environments and ensures code portability and reuse. This results in improved overall team productivity and greater predictability in the verification process. In addition, enhanced class-based debug utilities help manage the complexity of object-oriented testbench code. A new multi-language verification builder utility enables users to leverage existing templates, rapidly configure verification IP and accelerate early testbench development.
“Paradigm Works requires a robust, comprehensive solution when we deliver SystemVerilog-based chip design and verification services,” said Michael Hoyt, President and CEO of Paradigm Works. “Cadence Incisive Enterprise Simulator delivers the open class-based methodology, advanced debug, and powerful generation we need in our projects. We are using SystemVerilog with Cadence’s latest simulation software to raise the verification efficiency of both our engineers and those of our customers.”
Second-Generation Transaction-Based Acceleration
The Incisive Enterprise verification family delivers new capabilities to improve the productivity for system-level verification using Xtreme and Palladium hardware acceleration/emulation systems. A new version of Cadence TBA is compliant with the Accellera SCE-MI 2.0 draft standard, ensuring automation, ease of use and platform portability while delivering high performance. TBA 2.0 helps design and verification teams reduce their verification time by providing new infrastructure and guidelines to support reusable accelerated verification environment. The new TBA version combines methodology and product delivery, with a number of features that simplify the creation and debugging of transaction-based verification environments and verification IP, including: a native multi-language transaction-level modeling interface, automatic variable-length messaging, constraint randomization, automated transaction-level recording and powerful signal/transaction-level debugging capabilities.
“Cadence continues to introduce innovative technology coupled with advanced methodologies that address the needs of the most advanced verification teams,” said Jim Miller, Cadence executive vice president. “The new offerings in the Incisive Enterprise verification family enable our users to handle designs containing hundreds of millions of logic gates.”
Incisive Enterprise Simulator 6.2, Incisive Specman Testbench 6.2 and TBA 2.0-enabled Incisive Palladium and Incisive Xtreme systems are currently available.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,300 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, Incisive, Specman, Palladium, and Xtreme are registered trademarks, and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the U.S. and other countries.