Ambric Massively Parallel Processor Array Powers University Research

Ambric®, Inc., a fabless semiconductor company shipping the world’s first teraOPS-class chip that makes massively parallel software development practical for complex embedded systems, announced that three universities are now using Ambric’s massively parallel processor array (MPPA) technology in new, advanced research projects. The three institutions, which are charter members of the program, include the University of Washington and Portland State University in the U.S. and Sweden’s Halmstad University. Ambric is a privately held fabless semiconductor company headquartered in Beaverton, Ore., with funding from ComVentures, OVP Venture Partners, and Northwest Technology Ventures.

“We are very pleased to have these leading-edge universities as charter members of Ambric’s new University Program,” said Mike Butts, Ambric senior architect and Fellow. “These universities, and their distinguished professors and graduate students, are extending the boundaries of knowledge in massively parallel and embedded computing. The charter members are engaged in unique, advanced research in massively parallel software engineering, system partitioning, dynamically reprogrammable embedded systems, medical imaging, software-defined radios, computer vision, and advanced signal processing. Massively parallel computing will benefit not only from this close university and industry collaboration, but also from the unique Ambric structural object programming model and globally asynchronous silicon with 1.2 teraOPS and hundreds of processors. We are eager to see the results of their research projects.”

About Ambric’s University Program
The Ambric University Program was established to enable leading-edge, massively parallel processing technology for computer science engineering research and course curricula. Massively parallel processing is recognized as the only way to keep scaling processor technology to keep up with Moore’s Law over time. Universities that need to do research and educate engineers in massively parallel programming need a practical programming model, tools, boards, and reliable silicon with literally hundreds of different processors. Ambric’s family of Am2000(TM) MPPAs provides just that with its innovative globally asynchronous interconnect fabric, a process network(a) with bounded buffers. Ambric’s MPPA technology uniquely enables massively parallel research that otherwise would be difficult or impossible to accomplish. Initial installations of the hardware and software tools started in July of 2007 and projects are now being implemented with the technology.

Benefits of membership in the Ambric University Program include free or discounted access to Ambric’s massively parallel software development tools, Am2045(TM) MPPA developer boards with 344 processors and 1.2 teraOPS, and training. Universities interested in joining the program can contact Ambric by sending email with their name, university, country, research interests, and any questions to Mike Butts,

University of Washington
The sponsoring professor at the University of Washington, Professor Scott Hauck, is an associate professor in the Department of Electrical Engineering, and an adjunct professor in the Department of Computer Science and Engineering. He is also the director of the Adaptive Computing Machines and Emulators Lab. His work has been focused around FPGAs, chips that can be programmed and reprogrammed, using hardware description languages to implement complex digital logic. Domains of research have included medical imaging, image processing, reconfigurable subsystems, asynchronous circuits, design tool compilers, and system partitioning. Professors Hauck and Andre DeHon are editors of a just-released book on reconfigurable computing, entitled “Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation”, published by Morgan Kaufmann/Elsevier. Graduate students have already begun thesis work using Ambric MPPA technology and development tools.

Commented Professor Hauck, “The inability of general purpose processors to double their performance every eighteen months, as previously enabled by Moore’s law, has created new opportunities for massively parallel processing devices, especially for high-performance application domains. Reconfigurable architectures, such as Ambric’s, represent a sweet spot among FPGAs, ASICs, and DSPs, and may be the future of reconfigurable systems for streaming applications.”

Portland State University
The sponsoring professor at Portland State University is Professor Dan Hammerstrom, associate dean for the Research, Electrical and Computer Engineering Department, Maseeh College of Engineering and Computer Science. His research interests center on intelligent computing, based on applying lessons from biological systems. Difficult computer science problems involve the interaction of a system with the real world, which, in part, involves a transformation and understanding of data at the boundary between the real world and the digital world. Graduate students are currently engaged in research work using Ambric MPPA technology and development tools.

“Some of the toughest problems in computing science involve the interaction of a digital system with the real world,” said Professor Hammerstrom. “Examples include speech recognition, computer vision, textual and image content recognition, robotic control, unmanned vehicles, sensor data collection, intelligent power management, and optical character recognition. These problems are extremely compute-intensive, but they are also massively parallel. My students and I are very excited to use Ambric’s unique structural object programming model to see how some of these applications perform on this massively parallel computing platform.”

Halmstad University
Sponsoring the program at Halmstad University is Professor Bertil Svensson, who is the director of the Centre for Research on Embedded Systems (CERES), a joint university/industry research center for the development of technology and applications for embedded computer and communication systems. CERES is working in collaboration with industrial partners with applications that typically include high-performance or power-sensitive real-time data processing, or wireless dynamically connected sensors and actuators, or both. Eleven Swedish companies participate in CERES, including Ericsson and Volvo. Graduate students will begin research work using Ambric technology in January 2008.

According to Professor Svensson, “A general principle in CERES’ research is that functionality and performance are best achieved through the intelligent and massive cooperation among a large number of simple devices. For example, because of the downscaling following Moore’s law, massive co-operation between processing elements can be utilized on the micro level. This makes it possible to implement extremely high-performance, yet programmable, systems on a chip. The interconnections between the units at the chip, as well as at the board, level present challenging research questions. Consequently, Ambric’s massively parallel chip, with its hundreds of processing elements, is an attractive silicon platform for embedded systems research.”

About Ambric, Inc.
Ambric is a fabless semiconductor company that is shipping the world’s first teraOPS-class processor and tools that make massively parallel software programming practical for complex embedded systems. The company’s highly scalable, massively parallel processor arrays (MPPAs) deliver performance that is more than an order of magnitude higher than high-end DSPs. The price-performance exceeds that of FPGAs on complex applications while enabling faster, easier development in software. Ambric products help companies accelerate time-to-market for their solutions while slashing their system development costs. Established in 2003 and headquartered in Beaverton, Ore., Ambric has received funding from ComVentures, OVP Venture Partners, Northwest Technology Ventures, and private investors.

Ambric and the Ambric logo are registered trademarks, and Am2XXX is a trademark, of Ambric, Inc.

(a) Process networks (PNs) are a distributed model of computation (MoC) where a group of processing units are connected by communication channels to form a network of processes. PNs were originally developed for modeling distributed systems but have proven their convenience for modeling signal processing systems. PNs have been used in many applications modeling embedded systems. The Ambric MoC is based on Kahn Process Networks, introduced by Dr. Gilles Kahn, and on Professor Ed Lee’s more recent research on Dataflow Process Networks. The architecture of Ambric’s family of Am2000 MPPAs provides a PN MoC with its innovative, globally asynchronous, locally synchronous, massively parallel computing fabric, with hundreds of processors on a single chip and scalable to thousands of processors.