Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that Micronas has selected the Cadence® Incisive® Plan-to-Closure Methodology and Incisive Enterprise Manager for verification planning after a joint full functional verification audit helped discover and correct process flaws and areas of improvement for Micronas’ overall product development process. In addition, the audit helped bridge communications gaps and improve planning for various project development teams within differing times zones. As a result of the audit, Micronas chose Incisive Specman Elite® Testbench automation. Using Specman Elite’s automation capabilities supported Micronas’ wide efforts of reducing their design cycle times.
In this audit, the team at Micronas found several risk areas. The most significant improvement was that an intensive verification planning process early in the project would allow project managers to identify potential issues at the needed time, optimize resources, and track with an unified coverage data base the overall status of the verification process against the expected progress or initial plan. In addition, the audit led to more sharing of sub-system knowledge and configuration aspects of the designed device and top-level verification environment. In each of these instances, Micronas was able to identify suitable process changes with guidance from the Incisive Plan-to-Closure Methodology and implement the changes using the planning and management capabilities in Incisive Enterprise Manager combined with the automation of Incisive Specman Elite Testbench.
“Cadence helped us reevaluate our current verification development processes and identify opportunities to improve. The successful development of our recent line of 90-nanometer complex consumer video products, including pre-silicon Software verification on the Cadence® Incisive® Palladium® emulator system , proves that we’re on track,” said Oliver Bell, director of SoC methodology at Micronas. “We’ll continue improving and automating our development environment, one important cornerstone is feedback from external audits with partners like Cadence.”
Micronas found that a well-formulated verification environment should capture metrics throughout the lifetime of a project — including the development and integration of verification IP and assertion-based verification. By incorporating these activities into the verification plan, Micronas was able to speed the overall development of the RTL and the verification environment, which is extremely important for project development and ultimate success. Furthermore, the planning- and metric-driven approach offered the team guidance on how to better direct resources, thus increasing efficiency and providing control over the broader design and verification process.
“We’re thrilled to be working closely with Micronas to help them realize the many benefits of implementing a methodology that leverages verification automation, planning, and management,” said Michal Siwinski, group director of marketing at Cadence. “We’re confident that Micronas will continue to streamline their project development flow and we’ll continue to support their needs.”
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,300 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, Incisive and Specman are registered trademarks, and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the U.S. and other countries.