Tensilica®, Inc and eASIC Corporation announced a partnership to remove the cost barriers for developing custom embedded System-on-a-Chip (SoCs). Through this partnership eASIC now provides free access to Tensilica’s Diamond Standard microprocessor and digital signal processing (DSP) cores for its free mask charge, no-minimum order ASICs. This unique combination enables embedded system designers to develop Diamond processor-based SoCs for applications in any production volume. Designers will now be able to develop customized, highly differentiated ASIC solutions at a lower cost than FPGA-based embedded systems.
Tensilica’s processors range from a very small, low-power 32-bit controller up to the industry’s highest performance digital signal processing core and a multifunction audio processor that has been designed into millions of cellular phones. The Diamond Standard family includes:
- 106Micro – the industry’s smallest cacheless, 32-bit RISC controller core
- 108Mini – a small cacheless 32-bit RISC controller with built-in DSP capabilities
- 212GP – a flexible mid-range 32-bit RISC controller
- 232L – a mid-range 32-bit CPU with Memory Management Unit (MMU) for Linux OS support
- 570T – a high-end 32-bit CPU core
- 545CK – a high performance DSP core
- 330HiFi – a low-power, 24-bit audio DSP processor supported with popular audio and speech codecs
The Diamond Standard family covers the broadest range of performance of any embedded computing architecture and the processors are supported by an optimized set of Diamond Standard software tools and an extensive ecosystem of industry infrastructure partners. The Diamond Standard family is available to eASIC’s customers via the company’s eZ-IP Alliance program.
“Free Tensilica processors on zero-mask charge structured ASICs is a revolutionary breakthrough in reducing the upfront costs for customers looking to develop low-cost custom embedded processing systems at any volume,” stated Jasbinder Bhoot, senior director, Marketing at eASIC Corporation. “This partnership is proof that a new era of SOC is upon us. No upfront cost and no minimum order quantity for an embedded processor core on a high-performance and volume-capable ASIC.”
“Several of our customers have been attracted to eASIC’s Nextreme Structured ASICs for fast prototyping or mass production,” stated Chris Jones, Tensilica’s director of strategic alliances. “eASIC’s Structured ASIC technology offers customers a lower power, higher density solution than FPGAs at a much lower cost and faster time to market than cell-based ASICs.”
eASIC is a fabless semiconductor company offering breakthrough Structured ASIC devices that reduce the overall fabrication cost and time of customized silicon devices. Through employing a unique and patented combination of FPGA like logic-cells and via-layer customizable routing, eASIC enables customers to develop Structured ASICs with zero mask charges, no minimum order quantity and receive devices in under 4 weeks. Founded in 1999, eASIC Corporation is privately held, headquartered in Santa Clara, California. Investors include Vinod Khosla, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, and Evergreen Partners.
Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica’s low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support.
Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc.