Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, has developed unique test technologies enabling its customers, including Kawasaki Microelectronics (K-micro) and LSI Corporation, to more cost effectively produce large numbers of high-performance, super-dense integrated circuits with extremely high quality. Building a competitive processor or an advanced system on chip (SoC) ASIC design is a daunting technological challenge. Through its leading test generation and compression technology, Cadence® Encounter® Test technology helps ensure these complex, high-performance devices work as designed.
At companies like K-micro and LSI Corporation the drive to advanced process technologies is a key differentiating strategy. However, at these smaller geometries, the requirement for test coverage goes up dramatically, increasing both the time and cost of manufacturing test. In some cases, a single test program with high test coverage can add significant cost to a project, not just in test application time but also in the time it takes to develop and debug it. In the meantime, engineers struggle for a better way to avoid delivering defective chips to the market.
Cadence has made enormous advances to improve the quality of electronic devices through its inventive test methodology. Cadence has developed Encounter True-Time Test ATPG, which generates accelerated tests to rigorously exercise the design using on-product clock generation (OPCG) and faster-than-at-speed tests to find and eliminate small delay defects that might otherwise go undetected using traditional transition testing. Encounter True-Time Test ATPG also features unique timing-aware vector generation that uses SDF data to create vectors that are right by construction, as opposed to alternative solutions that do not use actual circuit timing. This results in more accurate vectors and fewer false failures, eliminating the need for time-consuming iterative debug and refinement to arrive at a good set of vectors.
Since many of today’s designs are extremely dense, the number of test patterns required to thoroughly test the entire chip could be too large for practical application on production test equipment. That’s why Cadence has also developed advanced Encounter Test compression technology—it reduces test volume and application time, and enables customers to achieve a high level of quality with shorter and less costly testing.
Cadence was able to demonstrate the value of Encounter Test compression technology and Encounter True-Time Test ATPG on a leading-edge DSP Processor design at LSI Corporation. The Encounter True-Time Test ATPG was able to generate effective test patterns to meet the quality needs of the LSI design team and improved defect containment within a fixed test data volume budget.
“Through the Cadence Encounter Test compression technology, and Encounter True-Time Test ATPG, we were able to meet our test data volume requirements with a highly effective set of tests,” said Technical Manager Rick Muscavage, DSP IC Design for LSI Corporation. “Our requirements were tough, including some very challenging scan structures not typically supported by other compression structures, but the expert Encounter Test support team came through for us.”
Similarly, Encounter Test allowed K-micro to embark on an advanced SoC design with significant amounts of embedded memory and multiple clock domains. To meet this challenge, and to improve the overall quality of their chip, K-micro deployed Encounter True-Time Test and heavily leveraged OPCG and test compression to successfully improve overall product quality.
“Encounter Test provides the capabilities K-micro requires to address design and test requirements for large, complex SoC products,” said Yoshito Muraishi, director of CAD development for Kawasaki Microelectronics. “Encounter True-Time Test ATPG achieved our stringent quality requirements for delay testing, and the compression structures allowed us to eliminate ‘x’-states caused by aggressive use of delay testing and still have a cost-effective test program.”
“Cadence Encounter Test compression technology and Encounter True-Time Test ATPG are proven technologies for testing advanced semiconductor designs,” said Sanjiv Taneja, vice president of Encounter Test R&D at Cadence. “This is a key combination to ensure highest quality while minimizing test cost for nanometer designs.”
Cadence will demonstrate both Encounter True-Time Test ATPG and Encounter Test compression technology at the International Test Conference (ITC) 2007, Santa Clara Convention Center, October 23-26, 2007.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence and Encounter are registered trademarks and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries.