Sequence Design to Host Low-Power Design Seminar in Japan

Sequence Design, EDA’s Design-For-Power (DFP) technology leader, will host its fifth low-power design seminar in Tokyo on Thursday, Nov. 8, 2007, from 12:50pm to 5:30pm at Tokyo’s Akihabara Convention Hall. This event is co-sponsored by Sequence Design, AMD Japan, Cadence Design Systems Japan, NEC System Technologies, and HP Japan.

The seminar focuses on reducing and managing power throughout the design flow.

Sequence Design’s President and CEO, Vic Kulkarni, will open the seminar with a corporate update and product strategy overview.

Keyynote Speech: Dr. Kimiyoshi Usami, a professor at Shibaura Institute of Technology, will speak on “Technology Trends in Low Power Design for SoCs.”

Fumihiro Minami, Group Manager of Toshiba Microelectronics Corporation will describe “How to Establish Appropriate Power Analysis Environments for SoCs.”

Karthikeyan, G.T., Senior Component Design Engineer, Intel Technology India Pvt. Ltd. will present on “Platform Level Power Simulation and Modeling Flow Using PowerTheater.”

Satoshi Kojima, Technical Marketing Director from NEC System Technologies, Ltd., will describe “Positioning of CyberWorkBench in ESL Design and its Roadmap.”

Sadao Suzuki, Sr. Technical Marketing Manager from Cadence Design Systems, Japan will present “Advanced Low Power Design with CPF.”

Hiroyuki Amano, Senior Manager, AMD Japan Ltd. will deliver the latest Opteron processor technology which supports HP server and workstation platforms.

Tom Miller, VP and GM at Sequence Design, will discuss Low Power Design and Optimization using Sequence products.

About Sequence
Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence Design-For-Power solutions give customers the competitive advantage necessary to excel in aggressive technology markets.